MLIR

Multi-Level IR Compiler Framework

'amdgpu' Dialect

The AMDGPU dialect provides wrappers around AMD-specific functionality and LLVM intrinsics. These wrappers should be used in conjunction with more generic dialects, such as gpu and vector, when generating LLVM IR that will eventually be executed on AMD hardware.

Operation definition 

amdgpu.raw_buffer_atomic_fadd (::mlir::amdgpu::RawBufferAtomicFaddOp) 

Raw Buffer Floating-point Atomic Add (MI-* only)

Syntax:

operation ::= `amdgpu.raw_buffer_atomic_fadd` attr-dict $value `->` $memref `[` $indices `]`
              (`sgprOffset` $sgprOffset^)? `:`
              type($value) `->` type($memref) `,` type($indices)

The amdgpu.raw_buffer_atomic_fadd op is a wrapper around the buffer-based atomic floating point addition available on the MI-* series of AMD GPUs.

The index into the buffer is computed as for memref.store with the addition of indexOffset (which is used to aid in emitting vectorized code) and, if present sgprOffset (which is added after bounds checks and includes any non-zero offset on the memref type).

All indexing components are given in terms of the memref’s element size, not the byte lengths required by the intrinsic.

Out of bounds atomic operations are ignored in hardware.

See amdgpu.raw_buffer_load for a description of how the underlying instruction is constructed.

Traits: AttrSizedOperandSegments

Attributes: 

AttributeMLIR TypeDescription
targetIsRDNA::mlir::BoolAttrbool attribute
boundsCheck::mlir::BoolAttrbool attribute
indexOffset::mlir::IntegerAttr32-bit signless integer attribute

Operands: 

OperandDescription
value32-bit float
memrefmemref of any type values
indices32-bit signless integer
sgprOffset32-bit signless integer

amdgpu.raw_buffer_load (::mlir::amdgpu::RawBufferLoadOp) 

Raw Buffer load, exposing GCN features

Syntax:

operation ::= `amdgpu.raw_buffer_load` attr-dict $memref `[` $indices `]`
              (`sgprOffset` $sgprOffset^)? `:`
              type($memref) `,` type($indices) `->` type($value)

The amdgpu.raw_buffer_load op is a wrapper around the buffer load intrinsics available on AMD GPUs, including extensions in newer GPUs.

The index into the buffer is computed as for memref.load with the additon of indexOffset and sgprOffset (which is added after bounds checks and includes any offset present on the memref type if it’s non-zero).

All indices and offsets are in units of the memref’s data type and are converted to bytes during lowering.

When a load is out of bounds, the instruction returns zero. Vector instructions bounds check each component’s address.

The memref struct is converted into a buffer resource (a V#) and the arguments are translated to intrinsic arguments as follows:

  • The base address of the buffer is the base address of the memref
  • The stride is 0 to enable raw mode
  • The number of records is the size of the memref, in bytes In the case of dynamically-shaped memrefs, this is computed at runtime as max_d (size(d) * stride(d)) * sizeof(elementType(memref))
  • The offset enable bit is 1, the index enable bit is 0.
  • The thread ID addition bit is off
  • If boundsCheck is false and the target is RDNA, OOB_SELECT is set to 2 to disable bounds checks, otherwise it is 0
  • The cache coherency bits are off
  • targetIsRDNA controls the setting of some reserved values that differ between RDNA and CDNA cores

Traits: AttrSizedOperandSegments

Attributes: 

AttributeMLIR TypeDescription
targetIsRDNA::mlir::BoolAttrbool attribute
boundsCheck::mlir::BoolAttrbool attribute
indexOffset::mlir::IntegerAttr32-bit signless integer attribute

Operands: 

OperandDescription
memrefmemref of any type values
indices32-bit signless integer
sgprOffset32-bit signless integer

Results: 

ResultDescription
valuebfloat16 type or 16-bit float or 32-bit float or 32-bit signless integer or 8-bit signless integer or vector of 32-bit float or 32-bit signless integer values of length 2/4 or vector of 16-bit float or bfloat16 type values of length 2/4/8 or vector of 8-bit signless integer values of length 2/4/8/16

amdgpu.raw_buffer_store (::mlir::amdgpu::RawBufferStoreOp) 

Raw Buffer Store, exposing GCN features

Syntax:

operation ::= `amdgpu.raw_buffer_store` attr-dict $value `->` $memref `[` $indices `]`
              (`sgprOffset` $sgprOffset^)? `:`
              type($value) `->` type($memref) `,` type($indices)

The amdgpu.raw_buffer_store op is a wrapper around the buffer store intrinsics available on AMD GPUs, including extensions in newer GPUs.

The store index is computed as in memref.store with the addition of indexOffset (which is included for uniformity with atomics and may be useful when writing vectorized code) and sgprOffset (which is added after bounds checks and implicitly includes the offset of the memref type if non-zero). All index components are in terms of the elements of the memref, not bytes, and are scaled up appropriately.

Out of bounds stores are ignored in hardware, including the out of bounds components of vector writes.

See amdgpu.raw_buffer_load for a description of how the underlying instruction is constructed.

Traits: AttrSizedOperandSegments

Attributes: 

AttributeMLIR TypeDescription
targetIsRDNA::mlir::BoolAttrbool attribute
boundsCheck::mlir::BoolAttrbool attribute
indexOffset::mlir::IntegerAttr32-bit signless integer attribute

Operands: 

OperandDescription
valuebfloat16 type or 16-bit float or 32-bit float or 32-bit signless integer or 8-bit signless integer or vector of 32-bit float or 32-bit signless integer values of length 2/4 or vector of 16-bit float or bfloat16 type values of length 2/4/8 or vector of 8-bit signless integer values of length 2/4/8/16
memrefmemref of any type values
indices32-bit signless integer
sgprOffset32-bit signless integer