MLIR

Multi-Level IR Compiler Framework

'arm_sve' Dialect

Basic dialect to target Arm SVE architectures This dialect contains the definitions necessary to target specific Arm SVE scalable vector operations.

Operation definition 

arm_sve.intr.fadd (::mlir::arm_sve::ScalableMaskedAddFIntrOp) 

Operands: 

OperandDescription
«unnamed»scalable vector of any type values
«unnamed»scalable vector of any type values
«unnamed»scalable vector of any type values

Results: 

ResultDescription
resLLVM dialect-compatible type

arm_sve.masked.addf (::mlir::arm_sve::ScalableMaskedAddFOp) 

masked addition for scalable vectors of floats

Syntax:

operation ::= `arm_sve.masked.addf` $mask `,` $src1 `,` $src2 attr-dict `:` type($mask) `,` type($res)

The arm_sve.masked.addf operation takes one scalable vector mask and two scalable vector operands, and perform floating point addition on active lanes. Inactive lanes will keep the value of the first operand. Traits: Commutative

Operands: 

OperandDescription
maskscalable vector of 1-bit signless integer values
src1scalable vector of floating-point values
src2scalable vector of floating-point values

Results: 

ResultDescription
resscalable vector of floating-point values

arm_sve.intr.add (::mlir::arm_sve::ScalableMaskedAddIIntrOp) 

Operands: 

OperandDescription
«unnamed»scalable vector of any type values
«unnamed»scalable vector of any type values
«unnamed»scalable vector of any type values

Results: 

ResultDescription
resLLVM dialect-compatible type

arm_sve.masked.addi (::mlir::arm_sve::ScalableMaskedAddIOp) 

masked addition for scalable vectors of integers

Syntax:

operation ::= `arm_sve.masked.addi` $mask `,` $src1 `,` $src2 attr-dict `:` type($mask) `,` type($res)

The arm_sve.masked.addi operation takes one scalable vector mask and two scalable vector operands, and perform integer addition on active lanes. Inactive lanes will keep the value of the first operand. Traits: Commutative

Operands: 

OperandDescription
maskscalable vector of 1-bit signless integer values
src1scalable vector of 8-bit signless integer or 16-bit signless integer or 32-bit signless integer or 64-bit signless integer values
src2scalable vector of 8-bit signless integer or 16-bit signless integer or 32-bit signless integer or 64-bit signless integer values

Results: 

ResultDescription
resscalable vector of 8-bit signless integer or 16-bit signless integer or 32-bit signless integer or 64-bit signless integer values

arm_sve.intr.fdiv (::mlir::arm_sve::ScalableMaskedDivFIntrOp) 

Operands: 

OperandDescription
«unnamed»scalable vector of any type values
«unnamed»scalable vector of any type values
«unnamed»scalable vector of any type values

Results: 

ResultDescription
resLLVM dialect-compatible type

arm_sve.masked.divf (::mlir::arm_sve::ScalableMaskedDivFOp) 

masked division for scalable vectors of floats

Syntax:

operation ::= `arm_sve.masked.divf` $mask `,` $src1 `,` $src2 attr-dict `:` type($mask) `,` type($res)

The arm_sve.masked.divf operation takes one scalable vector mask and two scalable vector operands, and perform floating point division on active lanes. Inactive lanes will keep the value of the first operand.

Operands: 

OperandDescription
maskscalable vector of 1-bit signless integer values
src1scalable vector of floating-point values
src2scalable vector of floating-point values

Results: 

ResultDescription
resscalable vector of floating-point values

arm_sve.intr.fmul (::mlir::arm_sve::ScalableMaskedMulFIntrOp) 

Operands: 

OperandDescription
«unnamed»scalable vector of any type values
«unnamed»scalable vector of any type values
«unnamed»scalable vector of any type values

Results: 

ResultDescription
resLLVM dialect-compatible type

arm_sve.masked.mulf (::mlir::arm_sve::ScalableMaskedMulFOp) 

masked multiplication for scalable vectors of floats

Syntax:

operation ::= `arm_sve.masked.mulf` $mask `,` $src1 `,` $src2 attr-dict `:` type($mask) `,` type($res)

The arm_sve.masked.mulf operation takes one scalable vector mask and two scalable vector operands, and perform floating point multiplication on active lanes. Inactive lanes will keep the value of the first operand. Traits: Commutative

Operands: 

OperandDescription
maskscalable vector of 1-bit signless integer values
src1scalable vector of floating-point values
src2scalable vector of floating-point values

Results: 

ResultDescription
resscalable vector of floating-point values

arm_sve.intr.mul (::mlir::arm_sve::ScalableMaskedMulIIntrOp) 

Operands: 

OperandDescription
«unnamed»scalable vector of any type values
«unnamed»scalable vector of any type values
«unnamed»scalable vector of any type values

Results: 

ResultDescription
resLLVM dialect-compatible type

arm_sve.masked.muli (::mlir::arm_sve::ScalableMaskedMulIOp) 

masked multiplication for scalable vectors of integers

Syntax:

operation ::= `arm_sve.masked.muli` $mask `,` $src1 `,` $src2 attr-dict `:` type($mask) `,` type($res)

The arm_sve.masked.muli operation takes one scalable vector mask and two scalable vector operands, and perform integer multiplication on active lanes. Inactive lanes will keep the value of the first operand. Traits: Commutative

Operands: 

OperandDescription
maskscalable vector of 1-bit signless integer values
src1scalable vector of 8-bit signless integer or 16-bit signless integer or 32-bit signless integer or 64-bit signless integer values
src2scalable vector of 8-bit signless integer or 16-bit signless integer or 32-bit signless integer or 64-bit signless integer values

Results: 

ResultDescription
resscalable vector of 8-bit signless integer or 16-bit signless integer or 32-bit signless integer or 64-bit signless integer values

arm_sve.intr.sdiv (::mlir::arm_sve::ScalableMaskedSDivIIntrOp) 

Operands: 

OperandDescription
«unnamed»scalable vector of any type values
«unnamed»scalable vector of any type values
«unnamed»scalable vector of any type values

Results: 

ResultDescription
resLLVM dialect-compatible type

arm_sve.masked.divi_signed (::mlir::arm_sve::ScalableMaskedSDivIOp) 

masked signed division for scalable vectors of integers

Syntax:

operation ::= `arm_sve.masked.divi_signed` $mask `,` $src1 `,` $src2 attr-dict `:` type($mask) `,` type($res)

The arm_sve.masked.divi_signed operation takes one scalable vector mask and two scalable vector operands, and perform integer signed division on active lanes. Inactive lanes will keep the value of the first operand.

Operands: 

OperandDescription
maskscalable vector of 1-bit signless integer values
src1scalable vector of 8-bit signless integer or 16-bit signless integer or 32-bit signless integer or 64-bit signless integer values
src2scalable vector of 8-bit signless integer or 16-bit signless integer or 32-bit signless integer or 64-bit signless integer values

Results: 

ResultDescription
resscalable vector of 8-bit signless integer or 16-bit signless integer or 32-bit signless integer or 64-bit signless integer values

arm_sve.intr.fsub (::mlir::arm_sve::ScalableMaskedSubFIntrOp) 

Operands: 

OperandDescription
«unnamed»scalable vector of any type values
«unnamed»scalable vector of any type values
«unnamed»scalable vector of any type values

Results: 

ResultDescription
resLLVM dialect-compatible type

arm_sve.masked.subf (::mlir::arm_sve::ScalableMaskedSubFOp) 

masked subtraction for scalable vectors of floats

Syntax:

operation ::= `arm_sve.masked.subf` $mask `,` $src1 `,` $src2 attr-dict `:` type($mask) `,` type($res)

The arm_sve.masked.subf operation takes one scalable vector mask and two scalable vector operands, and perform floating point subtraction on active lanes. Inactive lanes will keep the value of the first operand.

Operands: 

OperandDescription
maskscalable vector of 1-bit signless integer values
src1scalable vector of floating-point values
src2scalable vector of floating-point values

Results: 

ResultDescription
resscalable vector of floating-point values

arm_sve.intr.sub (::mlir::arm_sve::ScalableMaskedSubIIntrOp) 

Operands: 

OperandDescription
«unnamed»scalable vector of any type values
«unnamed»scalable vector of any type values
«unnamed»scalable vector of any type values

Results: 

ResultDescription
resLLVM dialect-compatible type

arm_sve.masked.subi (::mlir::arm_sve::ScalableMaskedSubIOp) 

masked subtraction for scalable vectors of integers

Syntax:

operation ::= `arm_sve.masked.subi` $mask `,` $src1 `,` $src2 attr-dict `:` type($mask) `,` type($res)

The arm_sve.masked.subi operation takes one scalable vector mask and two scalable vector operands, and perform integer subtraction on active lanes. Inactive lanes will keep the value of the first operand.

Operands: 

OperandDescription
maskscalable vector of 1-bit signless integer values
src1scalable vector of 8-bit signless integer or 16-bit signless integer or 32-bit signless integer or 64-bit signless integer values
src2scalable vector of 8-bit signless integer or 16-bit signless integer or 32-bit signless integer or 64-bit signless integer values

Results: 

ResultDescription
resscalable vector of 8-bit signless integer or 16-bit signless integer or 32-bit signless integer or 64-bit signless integer values

arm_sve.intr.udiv (::mlir::arm_sve::ScalableMaskedUDivIIntrOp) 

Operands: 

OperandDescription
«unnamed»scalable vector of any type values
«unnamed»scalable vector of any type values
«unnamed»scalable vector of any type values

Results: 

ResultDescription
resLLVM dialect-compatible type

arm_sve.masked.divi_unsigned (::mlir::arm_sve::ScalableMaskedUDivIOp) 

masked unsigned division for scalable vectors of integers

Syntax:

operation ::= `arm_sve.masked.divi_unsigned` $mask `,` $src1 `,` $src2 attr-dict `:` type($mask) `,` type($res)

The arm_sve.masked.divi_unsigned operation takes one scalable vector mask and two scalable vector operands, and perform integer unsigned division on active lanes. Inactive lanes will keep the value of the first operand.

Operands: 

OperandDescription
maskscalable vector of 1-bit signless integer values
src1scalable vector of 8-bit signless integer or 16-bit signless integer or 32-bit signless integer or 64-bit signless integer values
src2scalable vector of 8-bit signless integer or 16-bit signless integer or 32-bit signless integer or 64-bit signless integer values

Results: 

ResultDescription
resscalable vector of 8-bit signless integer or 16-bit signless integer or 32-bit signless integer or 64-bit signless integer values

arm_sve.intr.sdot (::mlir::arm_sve::SdotIntrOp) 

Operands: 

OperandDescription
«unnamed»scalable vector of any type values
«unnamed»scalable vector of any type values
«unnamed»scalable vector of any type values

Results: 

ResultDescription
resLLVM dialect-compatible type

arm_sve.sdot (::mlir::arm_sve::SdotOp) 

Vector-vector dot product and accumulate op

Syntax:

operation ::= `arm_sve.sdot` $acc `,` $src1 `,` $src2 attr-dict `:` type($src1) `to` type($dst)

SDOT: Signed integer addition of dot product.

This function maps to the SDOT instruction, and it takes signless integer operands that the operation interprets as signed. It partitions the second and third vector inputs into groups of four elements. They calculate the dot product of each group (without loss of precision) and then add each result to the overlapping element of the first vector input.

Source: https://developer.arm.com/documentation/100987/0000

Interfaces: NoSideEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands: 

OperandDescription
accscalable vector of 32-bit signless integer or 64-bit signless integer values of length 4/2
src1scalable vector of 8-bit signless integer or 16-bit signless integer values of length 16/8
src2scalable vector of 8-bit signless integer or 16-bit signless integer values of length 16/8

Results: 

ResultDescription
dstscalable vector of 32-bit signless integer or 64-bit signless integer values of length 4/2

arm_sve.intr.smmla (::mlir::arm_sve::SmmlaIntrOp) 

Operands: 

OperandDescription
«unnamed»scalable vector of any type values
«unnamed»scalable vector of any type values
«unnamed»scalable vector of any type values

Results: 

ResultDescription
resLLVM dialect-compatible type

arm_sve.smmla (::mlir::arm_sve::SmmlaOp) 

Matrix-matrix multiply and accumulate op

Syntax:

operation ::= `arm_sve.smmla` $acc `,` $src1 `,` $src2 attr-dict `:` type($src1) `to` type($dst)

SMMLA: Signed integer matrix multiply-accumulate.

This function maps to the SMMLA instruction, and it takes signless integer operands that the operation interprets as signed. It partitions the inputs into 128-bit quadwords, with the first input containing a row-by-row 2×2 matrix of 32-bit integers, the second input containing a row-by-row 2×8 matrix of 8-bit integers, and the third input containing a column-by-column 8×2 matrix of 8-bit integers. For each quadword, they multiply the second input matrix by the third input matrix using natural arithmetic and then add the result to the first input using modular arithmetic.

Source: https://developer.arm.com/documentation/100987/0000

Interfaces: NoSideEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands: 

OperandDescription
accscalable vector of 32-bit signless integer values of length 4
src1scalable vector of 8-bit signless integer values of length 16
src2scalable vector of 8-bit signless integer values of length 16

Results: 

ResultDescription
dstscalable vector of 32-bit signless integer values of length 4

arm_sve.intr.udot (::mlir::arm_sve::UdotIntrOp) 

Operands: 

OperandDescription
«unnamed»scalable vector of any type values
«unnamed»scalable vector of any type values
«unnamed»scalable vector of any type values

Results: 

ResultDescription
resLLVM dialect-compatible type

arm_sve.udot (::mlir::arm_sve::UdotOp) 

Vector-vector dot product and accumulate op

Syntax:

operation ::= `arm_sve.udot` $acc `,` $src1 `,` $src2 attr-dict `:` type($src1) `to` type($dst)

UDOT: Unsigned integer addition of dot product.

This function maps to the UDOT instruction, and it takes signless integer operands that the operation interprets as unsigned. It partitions the second and third vector inputs into groups of four elements. They calculate the dot product of each group (without loss of precision) and then add each result to the overlapping element of the first vector input.

Source: https://developer.arm.com/documentation/100987/0000

Interfaces: NoSideEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands: 

OperandDescription
accscalable vector of 32-bit signless integer or 64-bit signless integer values of length 4/2
src1scalable vector of 8-bit signless integer or 16-bit signless integer values of length 16/8
src2scalable vector of 8-bit signless integer or 16-bit signless integer values of length 16/8

Results: 

ResultDescription
dstscalable vector of 32-bit signless integer or 64-bit signless integer values of length 4/2

arm_sve.intr.ummla (::mlir::arm_sve::UmmlaIntrOp) 

Operands: 

OperandDescription
«unnamed»scalable vector of any type values
«unnamed»scalable vector of any type values
«unnamed»scalable vector of any type values

Results: 

ResultDescription
resLLVM dialect-compatible type

arm_sve.ummla (::mlir::arm_sve::UmmlaOp) 

Matrix-matrix multiply and accumulate op

Syntax:

operation ::= `arm_sve.ummla` $acc `,` $src1 `,` $src2 attr-dict `:` type($src1) `to` type($dst)

UMMLA: Unsigned integer matrix multiply-accumulate.

This function maps to the UMMLA instruction, and it takes signless integer operands that the operation interprets as unsigned. It partitions the inputs into 128-bit quadwords, with the first input containing a row-by-row 2×2 matrix of 32-bit integers, the second input containing a row-by-row 2×8 matrix of 8-bit integers, and the third input containing a column-by-column 8×2 matrix of 8-bit integers. For each quadword, they multiply the second input matrix by the third input matrix using natural arithmetic and then add the result to the first input using modular arithmetic.

Source: https://developer.arm.com/documentation/100987/0000

Interfaces: NoSideEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands: 

OperandDescription
accscalable vector of 32-bit signless integer values of length 4
src1scalable vector of 8-bit signless integer values of length 16
src2scalable vector of 8-bit signless integer values of length 16

Results: 

ResultDescription
dstscalable vector of 32-bit signless integer values of length 4