MLIR

Multi-Level IR Compiler Framework

'arm_sve' Dialect

Basic dialect to target Arm SVE architectures This dialect contains the definitions necessary to target Arm SVE scalable vector operations, including a scalable vector type and intrinsics for some Arm SVE instructions.

Type constraint definition 

scalable vector type 

arm_sve.vector represents vectors that will be processed by a scalable vector architecture.

Scalable vector type 

A type representing scalable length SIMD vectors. Unlike fixed-length SIMD vectors, whose size is constant and known at compile time, scalable vectors' length is constant but determined by the specific hardware at run time.

Operation definition 

arm_sve.addf (::mlir::arm_sve::ScalableAddFOp) 

addition for scalable vectors of floats

Syntax:

operation ::= `arm_sve.addf` $src1 `,` $src2 attr-dict `:` type($src1)

The arm_sve.addf operations takes two scalable vectors and returns one scalable vector with the result of the addition.

Operands: 

OperandDescription
src1scalable vector of floating-point values
src2scalable vector of floating-point values

Results: 

ResultDescription
dstscalable vector of floating-point values

arm_sve.addi (::mlir::arm_sve::ScalableAddIOp) 

addition for scalable vectors of integers

Syntax:

operation ::= `arm_sve.addi` $src1 `,` $src2 attr-dict `:` type($src1)

The arm_sve.addi operation takes two scalable vectors and returns one scalable vector with the result of the addition.

Operands: 

OperandDescription
src1scalable vector of 8-bit signless integer or 16-bit signless integer or 32-bit signless integer or 64-bit signless integer values
src2scalable vector of 8-bit signless integer or 16-bit signless integer or 32-bit signless integer or 64-bit signless integer values

Results: 

ResultDescription
dstscalable vector of 8-bit signless integer or 16-bit signless integer or 32-bit signless integer or 64-bit signless integer values

arm_sve.cmpf (::mlir::arm_sve::ScalableCmpFOp) 

floating-point comparison operation for scalable vectors

Syntax:

operation ::= `arm_sve.cmpf` $predicate `,` $lhs `,` $rhs attr-dict `:` type($lhs)

The arm_sve.cmpf operation compares two scalable vectors of floating point elements according to the float comparison rules and the predicate specified by the respective attribute. The predicate defines the type of comparison: (un)orderedness, (in)equality and signed less/greater than (or equal to) as well as predicates that are always true or false. The result is a scalable vector of i1 elements. Unlike arm_sve.cmpi, the operands are always treated as signed. The u prefix indicates unordered comparison, not unsigned comparison, so “une” means unordered not equal. For the sake of readability by humans, custom assembly form for the operation uses a string-typed attribute for the predicate. The value of this attribute corresponds to lower-cased name of the predicate constant, e.g., “one” means “ordered not equal”. The string representation of the attribute is merely a syntactic sugar and is converted to an integer attribute by the parser.

Example:

%r = arm_sve.cmpf oeq, %0, %1 : !arm_sve.vector<4xf32>

Attributes: 

AttributeMLIR TypeDescription
predicate::mlir::CmpFPredicateAttrallowed 64-bit signless integer cases: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15

Operands: 

OperandDescription
lhsscalable vector of floating-point values
rhsscalable vector of floating-point values

Results: 

ResultDescription
resultscalable vector of 1-bit signless integer values

arm_sve.cmpi (::mlir::arm_sve::ScalableCmpIOp) 

integer comparison operation for scalable vectors

Syntax:

operation ::= `arm_sve.cmpi` $predicate `,` $lhs `,` $rhs attr-dict `:` type($lhs)

The arm_sve.cmpi operation compares two scalable vectors of integer elements according to the predicate specified by the respective attribute.

The predicate defines the type of comparison:

  • equal (mnemonic: "eq"; integer value: 0)
  • not equal (mnemonic: "ne"; integer value: 1)
  • signed less than (mnemonic: "slt"; integer value: 2)
  • signed less than or equal (mnemonic: "sle"; integer value: 3)
  • signed greater than (mnemonic: "sgt"; integer value: 4)
  • signed greater than or equal (mnemonic: "sge"; integer value: 5)
  • unsigned less than (mnemonic: "ult"; integer value: 6)
  • unsigned less than or equal (mnemonic: "ule"; integer value: 7)
  • unsigned greater than (mnemonic: "ugt"; integer value: 8)
  • unsigned greater than or equal (mnemonic: "uge"; integer value: 9)

Example:

%r = arm_sve.cmpi uge, %0, %1 : !arm_sve.vector<4xi32>

Attributes: 

AttributeMLIR TypeDescription
predicate::mlir::CmpIPredicateAttrallowed 64-bit signless integer cases: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9

Operands: 

OperandDescription
lhsscalable vector of 8-bit signless integer or 16-bit signless integer or 32-bit signless integer or 64-bit signless integer values
rhsscalable vector of 8-bit signless integer or 16-bit signless integer or 32-bit signless integer or 64-bit signless integer values

Results: 

ResultDescription
resultscalable vector of 1-bit signless integer values

arm_sve.divf (::mlir::arm_sve::ScalableDivFOp) 

division for scalable vectors of floats

Syntax:

operation ::= `arm_sve.divf` $src1 `,` $src2 attr-dict `:` type($src1)

The arm_sve.divf operations takes two scalable vectors and returns one scalable vector with the result of the division.

Operands: 

OperandDescription
src1scalable vector of floating-point values
src2scalable vector of floating-point values

Results: 

ResultDescription
dstscalable vector of floating-point values

arm_sve.load (::mlir::arm_sve::ScalableLoadOp) 

Load scalable vector from memory

Syntax:

operation ::= `arm_sve.load` $base `[` $index `]` attr-dict `:` type($result) `from` type($base)

Load a slice of memory into a scalable vector.

Operands: 

OperandDescription
basememref of any type values
indexindex

Results: 

ResultDescription
resultscalable vector of any type values

arm_sve.intr.fadd (::mlir::arm_sve::ScalableMaskedAddFIntrOp) 

Operands: 

OperandDescription
«unnamed»LLVM dialect scalable vector type
«unnamed»LLVM dialect scalable vector type
«unnamed»LLVM dialect scalable vector type

Results: 

ResultDescription
resLLVM dialect-compatible type

arm_sve.masked.addf (::mlir::arm_sve::ScalableMaskedAddFOp) 

masked addition for scalable vectors of floats

Syntax:

operation ::= `arm_sve.masked.addf` $mask `,` $src1 `,` $src2 attr-dict `:` type($mask) `,` type($res)

The arm_sve.masked.addf operation takes one scalable vector mask and two scalable vector operands, and perform floating point addition on active lanes. Inactive lanes will keep the value of the first operand.

Operands: 

OperandDescription
maskscalable vector of 1-bit signless integer values
src1scalable vector of floating-point values
src2scalable vector of floating-point values

Results: 

ResultDescription
resscalable vector of floating-point values

arm_sve.intr.add (::mlir::arm_sve::ScalableMaskedAddIIntrOp) 

Operands: 

OperandDescription
«unnamed»LLVM dialect scalable vector type
«unnamed»LLVM dialect scalable vector type
«unnamed»LLVM dialect scalable vector type

Results: 

ResultDescription
resLLVM dialect-compatible type

arm_sve.masked.addi (::mlir::arm_sve::ScalableMaskedAddIOp) 

masked addition for scalable vectors of integers

Syntax:

operation ::= `arm_sve.masked.addi` $mask `,` $src1 `,` $src2 attr-dict `:` type($mask) `,` type($res)

The arm_sve.masked.addi operation takes one scalable vector mask and two scalable vector operands, and perform integer addition on active lanes. Inactive lanes will keep the value of the first operand.

Operands: 

OperandDescription
maskscalable vector of 1-bit signless integer values
src1scalable vector of 8-bit signless integer or 16-bit signless integer or 32-bit signless integer or 64-bit signless integer values
src2scalable vector of 8-bit signless integer or 16-bit signless integer or 32-bit signless integer or 64-bit signless integer values

Results: 

ResultDescription
resscalable vector of 8-bit signless integer or 16-bit signless integer or 32-bit signless integer or 64-bit signless integer values

arm_sve.intr.fdiv (::mlir::arm_sve::ScalableMaskedDivFIntrOp) 

Operands: 

OperandDescription
«unnamed»LLVM dialect scalable vector type
«unnamed»LLVM dialect scalable vector type
«unnamed»LLVM dialect scalable vector type

Results: 

ResultDescription
resLLVM dialect-compatible type

arm_sve.masked.divf (::mlir::arm_sve::ScalableMaskedDivFOp) 

masked division for scalable vectors of floats

Syntax:

operation ::= `arm_sve.masked.divf` $mask `,` $src1 `,` $src2 attr-dict `:` type($mask) `,` type($res)

The arm_sve.masked.divf operation takes one scalable vector mask and two scalable vector operands, and perform floating point division on active lanes. Inactive lanes will keep the value of the first operand.

Operands: 

OperandDescription
maskscalable vector of 1-bit signless integer values
src1scalable vector of floating-point values
src2scalable vector of floating-point values

Results: 

ResultDescription
resscalable vector of floating-point values

arm_sve.intr.fmul (::mlir::arm_sve::ScalableMaskedMulFIntrOp) 

Operands: 

OperandDescription
«unnamed»LLVM dialect scalable vector type
«unnamed»LLVM dialect scalable vector type
«unnamed»LLVM dialect scalable vector type

Results: 

ResultDescription
resLLVM dialect-compatible type

arm_sve.masked.mulf (::mlir::arm_sve::ScalableMaskedMulFOp) 

masked multiplication for scalable vectors of floats

Syntax:

operation ::= `arm_sve.masked.mulf` $mask `,` $src1 `,` $src2 attr-dict `:` type($mask) `,` type($res)

The arm_sve.masked.mulf operation takes one scalable vector mask and two scalable vector operands, and perform floating point multiplication on active lanes. Inactive lanes will keep the value of the first operand.

Operands: 

OperandDescription
maskscalable vector of 1-bit signless integer values
src1scalable vector of floating-point values
src2scalable vector of floating-point values

Results: 

ResultDescription
resscalable vector of floating-point values

arm_sve.intr.mul (::mlir::arm_sve::ScalableMaskedMulIIntrOp) 

Operands: 

OperandDescription
«unnamed»LLVM dialect scalable vector type
«unnamed»LLVM dialect scalable vector type
«unnamed»LLVM dialect scalable vector type

Results: 

ResultDescription
resLLVM dialect-compatible type

arm_sve.masked.muli (::mlir::arm_sve::ScalableMaskedMulIOp) 

masked multiplication for scalable vectors of integers

Syntax:

operation ::= `arm_sve.masked.muli` $mask `,` $src1 `,` $src2 attr-dict `:` type($mask) `,` type($res)

The arm_sve.masked.muli operation takes one scalable vector mask and two scalable vector operands, and perform integer multiplication on active lanes. Inactive lanes will keep the value of the first operand.

Operands: 

OperandDescription
maskscalable vector of 1-bit signless integer values
src1scalable vector of 8-bit signless integer or 16-bit signless integer or 32-bit signless integer or 64-bit signless integer values
src2scalable vector of 8-bit signless integer or 16-bit signless integer or 32-bit signless integer or 64-bit signless integer values

Results: 

ResultDescription
resscalable vector of 8-bit signless integer or 16-bit signless integer or 32-bit signless integer or 64-bit signless integer values

arm_sve.intr.sdiv (::mlir::arm_sve::ScalableMaskedSDivIIntrOp) 

Operands: 

OperandDescription
«unnamed»LLVM dialect scalable vector type
«unnamed»LLVM dialect scalable vector type
«unnamed»LLVM dialect scalable vector type

Results: 

ResultDescription
resLLVM dialect-compatible type

arm_sve.masked.divi_signed (::mlir::arm_sve::ScalableMaskedSDivIOp) 

masked signed division for scalable vectors of integers

Syntax:

operation ::= `arm_sve.masked.divi_signed` $mask `,` $src1 `,` $src2 attr-dict `:` type($mask) `,` type($res)

The arm_sve.masked.divi_signed operation takes one scalable vector mask and two scalable vector operands, and perform integer signed division on active lanes. Inactive lanes will keep the value of the first operand.

Operands: 

OperandDescription
maskscalable vector of 1-bit signless integer values
src1scalable vector of 8-bit signless integer or 16-bit signless integer or 32-bit signless integer or 64-bit signless integer values
src2scalable vector of 8-bit signless integer or 16-bit signless integer or 32-bit signless integer or 64-bit signless integer values

Results: 

ResultDescription
resscalable vector of 8-bit signless integer or 16-bit signless integer or 32-bit signless integer or 64-bit signless integer values

arm_sve.intr.fsub (::mlir::arm_sve::ScalableMaskedSubFIntrOp) 

Operands: 

OperandDescription
«unnamed»LLVM dialect scalable vector type
«unnamed»LLVM dialect scalable vector type
«unnamed»LLVM dialect scalable vector type

Results: 

ResultDescription
resLLVM dialect-compatible type

arm_sve.masked.subf (::mlir::arm_sve::ScalableMaskedSubFOp) 

masked subtraction for scalable vectors of floats

Syntax:

operation ::= `arm_sve.masked.subf` $mask `,` $src1 `,` $src2 attr-dict `:` type($mask) `,` type($res)

The arm_sve.masked.subf operation takes one scalable vector mask and two scalable vector operands, and perform floating point subtraction on active lanes. Inactive lanes will keep the value of the first operand.

Operands: 

OperandDescription
maskscalable vector of 1-bit signless integer values
src1scalable vector of floating-point values
src2scalable vector of floating-point values

Results: 

ResultDescription
resscalable vector of floating-point values

arm_sve.intr.sub (::mlir::arm_sve::ScalableMaskedSubIIntrOp) 

Operands: 

OperandDescription
«unnamed»LLVM dialect scalable vector type
«unnamed»LLVM dialect scalable vector type
«unnamed»LLVM dialect scalable vector type

Results: 

ResultDescription
resLLVM dialect-compatible type

arm_sve.masked.subi (::mlir::arm_sve::ScalableMaskedSubIOp) 

masked subtraction for scalable vectors of integers

Syntax:

operation ::= `arm_sve.masked.subi` $mask `,` $src1 `,` $src2 attr-dict `:` type($mask) `,` type($res)

The arm_sve.masked.subi operation takes one scalable vector mask and two scalable vector operands, and perform integer subtraction on active lanes. Inactive lanes will keep the value of the first operand.

Operands: 

OperandDescription
maskscalable vector of 1-bit signless integer values
src1scalable vector of 8-bit signless integer or 16-bit signless integer or 32-bit signless integer or 64-bit signless integer values
src2scalable vector of 8-bit signless integer or 16-bit signless integer or 32-bit signless integer or 64-bit signless integer values

Results: 

ResultDescription
resscalable vector of 8-bit signless integer or 16-bit signless integer or 32-bit signless integer or 64-bit signless integer values

arm_sve.intr.udiv (::mlir::arm_sve::ScalableMaskedUDivIIntrOp) 

Operands: 

OperandDescription
«unnamed»LLVM dialect scalable vector type
«unnamed»LLVM dialect scalable vector type
«unnamed»LLVM dialect scalable vector type

Results: 

ResultDescription
resLLVM dialect-compatible type

arm_sve.masked.divi_unsigned (::mlir::arm_sve::ScalableMaskedUDivIOp) 

masked unsigned division for scalable vectors of integers

Syntax:

operation ::= `arm_sve.masked.divi_unsigned` $mask `,` $src1 `,` $src2 attr-dict `:` type($mask) `,` type($res)

The arm_sve.masked.divi_unsigned operation takes one scalable vector mask and two scalable vector operands, and perform integer unsigned division on active lanes. Inactive lanes will keep the value of the first operand.

Operands: 

OperandDescription
maskscalable vector of 1-bit signless integer values
src1scalable vector of 8-bit signless integer or 16-bit signless integer or 32-bit signless integer or 64-bit signless integer values
src2scalable vector of 8-bit signless integer or 16-bit signless integer or 32-bit signless integer or 64-bit signless integer values

Results: 

ResultDescription
resscalable vector of 8-bit signless integer or 16-bit signless integer or 32-bit signless integer or 64-bit signless integer values

arm_sve.mulf (::mlir::arm_sve::ScalableMulFOp) 

multiplication for scalable vectors of floats

Syntax:

operation ::= `arm_sve.mulf` $src1 `,` $src2 attr-dict `:` type($src1)

The arm_sve.mulf operations takes two scalable vectors and returns one scalable vector with the result of the multiplication.

Operands: 

OperandDescription
src1scalable vector of floating-point values
src2scalable vector of floating-point values

Results: 

ResultDescription
dstscalable vector of floating-point values

arm_sve.muli (::mlir::arm_sve::ScalableMulIOp) 

multiplication for scalable vectors of integers

Syntax:

operation ::= `arm_sve.muli` $src1 `,` $src2 attr-dict `:` type($src1)

The arm_sve.muli operation takes two scalable vectors and returns one scalable vector with the result of the multiplication.

Operands: 

OperandDescription
src1scalable vector of 8-bit signless integer or 16-bit signless integer or 32-bit signless integer or 64-bit signless integer values
src2scalable vector of 8-bit signless integer or 16-bit signless integer or 32-bit signless integer or 64-bit signless integer values

Results: 

ResultDescription
dstscalable vector of 8-bit signless integer or 16-bit signless integer or 32-bit signless integer or 64-bit signless integer values

arm_sve.divi_signed (::mlir::arm_sve::ScalableSDivIOp) 

signed division for scalable vectors of integers

Syntax:

operation ::= `arm_sve.divi_signed` $src1 `,` $src2 attr-dict `:` type($src1)

The arm_sve.divi_signed operation takes two scalable vectors and returns one scalable vector with the result of the signed division.

Operands: 

OperandDescription
src1scalable vector of 8-bit signless integer or 16-bit signless integer or 32-bit signless integer or 64-bit signless integer values
src2scalable vector of 8-bit signless integer or 16-bit signless integer or 32-bit signless integer or 64-bit signless integer values

Results: 

ResultDescription
dstscalable vector of 8-bit signless integer or 16-bit signless integer or 32-bit signless integer or 64-bit signless integer values

arm_sve.store (::mlir::arm_sve::ScalableStoreOp) 

Store scalable vector into memory

Syntax:

operation ::= `arm_sve.store` $value `,` $base `[` $index `]` attr-dict `:` type($value) `to` type($base)

Store a scalable vector on a slice of memory.

Operands: 

OperandDescription
basememref of any type values
indexindex
valuescalable vector of any type values

arm_sve.subf (::mlir::arm_sve::ScalableSubFOp) 

subtraction for scalable vectors of floats

Syntax:

operation ::= `arm_sve.subf` $src1 `,` $src2 attr-dict `:` type($src1)

The arm_sve.subf operations takes two scalable vectors and returns one scalable vector with the result of the subtraction.

Operands: 

OperandDescription
src1scalable vector of floating-point values
src2scalable vector of floating-point values

Results: 

ResultDescription
dstscalable vector of floating-point values

arm_sve.subi (::mlir::arm_sve::ScalableSubIOp) 

subtraction for scalable vectors of integers

Syntax:

operation ::= `arm_sve.subi` $src1 `,` $src2 attr-dict `:` type($src1)

The arm_sve.subi operation takes two scalable vectors and returns one scalable vector with the result of the subtraction.

Operands: 

OperandDescription
src1scalable vector of 8-bit signless integer or 16-bit signless integer or 32-bit signless integer or 64-bit signless integer values
src2scalable vector of 8-bit signless integer or 16-bit signless integer or 32-bit signless integer or 64-bit signless integer values

Results: 

ResultDescription
dstscalable vector of 8-bit signless integer or 16-bit signless integer or 32-bit signless integer or 64-bit signless integer values

arm_sve.divi_unsigned (::mlir::arm_sve::ScalableUDivIOp) 

unsigned division for scalable vectors of integers

Syntax:

operation ::= `arm_sve.divi_unsigned` $src1 `,` $src2 attr-dict `:` type($src1)

The arm_sve.divi_unsigned operation takes two scalable vectors and returns one scalable vector with the result of the unsigned division.

Operands: 

OperandDescription
src1scalable vector of 8-bit signless integer or 16-bit signless integer or 32-bit signless integer or 64-bit signless integer values
src2scalable vector of 8-bit signless integer or 16-bit signless integer or 32-bit signless integer or 64-bit signless integer values

Results: 

ResultDescription
dstscalable vector of 8-bit signless integer or 16-bit signless integer or 32-bit signless integer or 64-bit signless integer values

arm_sve.intr.sdot (::mlir::arm_sve::SdotIntrOp) 

Operands: 

OperandDescription
«unnamed»LLVM dialect scalable vector type
«unnamed»LLVM dialect scalable vector type
«unnamed»LLVM dialect scalable vector type

Results: 

ResultDescription
resLLVM dialect-compatible type

arm_sve.sdot (::mlir::arm_sve::SdotOp) 

Vector-vector dot product and accumulate op

Syntax:

operation ::= `arm_sve.sdot` $acc `,` $src1 `,` $src2 attr-dict `:` type($src1) `to` type($dst)

SDOT: Signed integer addition of dot product.

This function maps to the SDOT instruction, and it takes signless integer operands that the operation interprets as signed. It partitions the second and third vector inputs into groups of four elements. They calculate the dot product of each group (without loss of precision) and then add each result to the overlapping element of the first vector input.

Source: https://developer.arm.com/documentation/100987/0000

Operands: 

OperandDescription
accscalable vector of 32-bit signless integer or 64-bit signless integer values of length 4/2
src1scalable vector of 8-bit signless integer or 16-bit signless integer values of length 16/8
src2scalable vector of 8-bit signless integer or 16-bit signless integer values of length 16/8

Results: 

ResultDescription
dstscalable vector of 32-bit signless integer or 64-bit signless integer values of length 4/2

arm_sve.intr.smmla (::mlir::arm_sve::SmmlaIntrOp) 

Operands: 

OperandDescription
«unnamed»LLVM dialect scalable vector type
«unnamed»LLVM dialect scalable vector type
«unnamed»LLVM dialect scalable vector type

Results: 

ResultDescription
resLLVM dialect-compatible type

arm_sve.smmla (::mlir::arm_sve::SmmlaOp) 

Matrix-matrix multiply and accumulate op

Syntax:

operation ::= `arm_sve.smmla` $acc `,` $src1 `,` $src2 attr-dict `:` type($src1) `to` type($dst)

SMMLA: Signed integer matrix multiply-accumulate.

This function maps to the SMMLA instruction, and it takes signless integer operands that the operation interprets as signed. It partitions the inputs into 128-bit quadwords, with the first input containing a row-by-row 2×2 matrix of 32-bit integers, the second input containing a row-by-row 2×8 matrix of 8-bit integers, and the third input containing a column-by-column 8×2 matrix of 8-bit integers. For each quadword, they multiply the second input matrix by the third input matrix using natural arithmetic and then add the result to the first input using modular arithmetic.

Source: https://developer.arm.com/documentation/100987/0000

Operands: 

OperandDescription
accscalable vector of 32-bit signless integer values of length 4
src1scalable vector of 8-bit signless integer values of length 16
src2scalable vector of 8-bit signless integer values of length 16

Results: 

ResultDescription
dstscalable vector of 32-bit signless integer values of length 4

arm_sve.intr.udot (::mlir::arm_sve::UdotIntrOp) 

Operands: 

OperandDescription
«unnamed»LLVM dialect scalable vector type
«unnamed»LLVM dialect scalable vector type
«unnamed»LLVM dialect scalable vector type

Results: 

ResultDescription
resLLVM dialect-compatible type

arm_sve.udot (::mlir::arm_sve::UdotOp) 

Vector-vector dot product and accumulate op

Syntax:

operation ::= `arm_sve.udot` $acc `,` $src1 `,` $src2 attr-dict `:` type($src1) `to` type($dst)

UDOT: Unsigned integer addition of dot product.

This function maps to the UDOT instruction, and it takes signless integer operands that the operation interprets as unsigned. It partitions the second and third vector inputs into groups of four elements. They calculate the dot product of each group (without loss of precision) and then add each result to the overlapping element of the first vector input.

Source: https://developer.arm.com/documentation/100987/0000

Operands: 

OperandDescription
accscalable vector of 32-bit signless integer or 64-bit signless integer values of length 4/2
src1scalable vector of 8-bit signless integer or 16-bit signless integer values of length 16/8
src2scalable vector of 8-bit signless integer or 16-bit signless integer values of length 16/8

Results: 

ResultDescription
dstscalable vector of 32-bit signless integer or 64-bit signless integer values of length 4/2

arm_sve.intr.ummla (::mlir::arm_sve::UmmlaIntrOp) 

Operands: 

OperandDescription
«unnamed»LLVM dialect scalable vector type
«unnamed»LLVM dialect scalable vector type
«unnamed»LLVM dialect scalable vector type

Results: 

ResultDescription
resLLVM dialect-compatible type

arm_sve.ummla (::mlir::arm_sve::UmmlaOp) 

Matrix-matrix multiply and accumulate op

Syntax:

operation ::= `arm_sve.ummla` $acc `,` $src1 `,` $src2 attr-dict `:` type($src1) `to` type($dst)

UMMLA: Unsigned integer matrix multiply-accumulate.

This function maps to the UMMLA instruction, and it takes signless integer operands that the operation interprets as unsigned. It partitions the inputs into 128-bit quadwords, with the first input containing a row-by-row 2×2 matrix of 32-bit integers, the second input containing a row-by-row 2×8 matrix of 8-bit integers, and the third input containing a column-by-column 8×2 matrix of 8-bit integers. For each quadword, they multiply the second input matrix by the third input matrix using natural arithmetic and then add the result to the first input using modular arithmetic.

Source: https://developer.arm.com/documentation/100987/0000

Operands: 

OperandDescription
accscalable vector of 32-bit signless integer values of length 4
src1scalable vector of 8-bit signless integer values of length 16
src2scalable vector of 8-bit signless integer values of length 16

Results: 

ResultDescription
dstscalable vector of 32-bit signless integer values of length 4

arm_sve.vscale (::mlir::arm_sve::VectorScaleIntrOp) 

Results: 

ResultDescription
resLLVM dialect-compatible type

arm_sve.vector_scale (::mlir::arm_sve::VectorScaleOp) 

Load vector scale size

Syntax:

operation ::= `arm_sve.vector_scale` attr-dict `:` type($res)

The vector_scale op returns the scale of the scalable vectors, a positive integer value that is constant at runtime but unknown at compile time. The scale of the vector indicates the multiplicity of the vectors and vector operations. I.e.: an !arm_sve.vector<4xi32> is equivalent to vector_scale consecutive vector<4xi32>; and an operation on an !arm_sve.vector<4xi32> is equivalent to performing that operation vector_scale times, once on each <4xi32> segment of the scalable vector. The vector_scale op can be used to calculate the step in vector-length agnostic (VLA) loops.

Results: 

ResultDescription
resindex

Type definition 

ScalableVectorType 

Scalable vector type

A type representing scalable length SIMD vectors. Unlike fixed-length SIMD vectors, whose size is constant and known at compile time, scalable vectors' length is constant but determined by the specific hardware at run time.

Parameters: 

ParameterC++ typeDescription
shape::llvm::ArrayRef<int64_t>Vector shape
elementTypeType