MLIR

Multi-Level IR Compiler Framework

'arm_sve' Dialect

Basic dialect to target Arm SVE architectures This dialect contains the definitions necessary to target Arm SVE scalable vector operations, including a scalable vector type and intrinsics for some Arm SVE instructions.

Type constraint definition 

scalable vector type 

arm_sve.vector represents vectors that will be processed by a scalable vector architecture.

Scalable vector type 

A type representing scalable length SIMD vectors. Unlike fixed-length SIMD vectors, whose size is constant and known at compile time, scalable vectors’ length is constant but determined by the specific hardware at run time.

Operation definition 

arm_sve.sdot (::mlir::arm_sve::SdotOp) 

Vector-vector dot product and accumulate op

Syntax:

operation ::= `arm_sve.sdot` $acc `,` $src1 `,` $src2 attr-dict `:` type($src1) `to` type($dst)

SDOT: Signed integer addition of dot product.

This function maps to the SDOT instruction, and it takes signless integer operands that the operation interprets as signed. It partitions the second and third vector inputs into groups of four elements. They calculate the dot product of each group (without loss of precision) and then add each result to the overlapping element of the first vector input.

Source: https://developer.arm.com/documentation/100987/0000

Operands: 

OperandDescription
accscalable vector of 32-bit signless integer or 64-bit signless integer values of length 4/2
src1scalable vector of 8-bit signless integer or 16-bit signless integer values of length 16/8
src2scalable vector of 8-bit signless integer or 16-bit signless integer values of length 16/8

Results: 

ResultDescription
dstscalable vector of 32-bit signless integer or 64-bit signless integer values of length 4/2

arm_sve.smmla (::mlir::arm_sve::SmmlaOp) 

Matrix-matrix multiply and accumulate op

Syntax:

operation ::= `arm_sve.smmla` $acc `,` $src1 `,` $src2 attr-dict `:` type($src1) `to` type($dst)

SMMLA: Signed integer matrix multiply-accumulate.

This function maps to the SMMLA instruction, and it takes signless integer operands that the operation interprets as signed. It partitions the inputs into 128-bit quadwords, with the first input containing a row-by-row 2×2 matrix of 32-bit integers, the second input containing a row-by-row 2×8 matrix of 8-bit integers, and the third input containing a column-by-column 8×2 matrix of 8-bit integers. For each quadword, they multiply the second input matrix by the third input matrix using natural arithmetic and then add the result to the first input using modular arithmetic.

Source: https://developer.arm.com/documentation/100987/0000

Operands: 

OperandDescription
accscalable vector of 32-bit signless integer values of length 4
src1scalable vector of 8-bit signless integer values of length 16
src2scalable vector of 8-bit signless integer values of length 16

Results: 

ResultDescription
dstscalable vector of 32-bit signless integer values of length 4

arm_sve.udot (::mlir::arm_sve::UdotOp) 

Vector-vector dot product and accumulate op

Syntax:

operation ::= `arm_sve.udot` $acc `,` $src1 `,` $src2 attr-dict `:` type($src1) `to` type($dst)

UDOT: Unsigned integer addition of dot product.

This function maps to the UDOT instruction, and it takes signless integer operands that the operation interprets as unsigned. It partitions the second and third vector inputs into groups of four elements. They calculate the dot product of each group (without loss of precision) and then add each result to the overlapping element of the first vector input.

Source: https://developer.arm.com/documentation/100987/0000

Operands: 

OperandDescription
accscalable vector of 32-bit signless integer or 64-bit signless integer values of length 4/2
src1scalable vector of 8-bit signless integer or 16-bit signless integer values of length 16/8
src2scalable vector of 8-bit signless integer or 16-bit signless integer values of length 16/8

Results: 

ResultDescription
dstscalable vector of 32-bit signless integer or 64-bit signless integer values of length 4/2

arm_sve.ummla (::mlir::arm_sve::UmmlaOp) 

Matrix-matrix multiply and accumulate op

Syntax:

operation ::= `arm_sve.ummla` $acc `,` $src1 `,` $src2 attr-dict `:` type($src1) `to` type($dst)

UMMLA: Unsigned integer matrix multiply-accumulate.

This function maps to the UMMLA instruction, and it takes signless integer operands that the operation interprets as unsigned. It partitions the inputs into 128-bit quadwords, with the first input containing a row-by-row 2×2 matrix of 32-bit integers, the second input containing a row-by-row 2×8 matrix of 8-bit integers, and the third input containing a column-by-column 8×2 matrix of 8-bit integers. For each quadword, they multiply the second input matrix by the third input matrix using natural arithmetic and then add the result to the first input using modular arithmetic.

Source: https://developer.arm.com/documentation/100987/0000

Operands: 

OperandDescription
accscalable vector of 32-bit signless integer values of length 4
src1scalable vector of 8-bit signless integer values of length 16
src2scalable vector of 8-bit signless integer values of length 16

Results: 

ResultDescription
dstscalable vector of 32-bit signless integer values of length 4

arm_sve.vector_scale (::mlir::arm_sve::VectorScaleOp) 

Load vector scale size

Syntax:

operation ::= `arm_sve.vector_scale` attr-dict `:` type($res)

The vector_scale op returns the scale of the scalable vectors, a positive integer value that is constant at runtime but unknown at compile time. The scale of the vector indicates the multiplicity of the vectors and vector operations. I.e.: an !arm_sve.vector<4xi32> is equivalent to vector_scale consecutive vector<4xi32>; and an operation on an !arm_sve.vector<4xi32> is equivalent to performing that operation vector_scale times, once on each <4xi32> segment of the scalable vector. The vector_scale op can be used to calculate the step in vector-length agnostic (VLA) loops.

Results: 

ResultDescription
resindex

Type definition 

ScalableVectorType (ScalableVectorType) 

Scalable vector type A type representing scalable length SIMD vectors. Unlike fixed-length SIMD vectors, whose size is constant and known at compile time, scalable vectors’ length is constant but determined by the specific hardware at run time.

Type parameters: 

ParameterC++ typeDescription
shapeScalableVectorTypeVector shape
elementTypeScalableVectorType