MLIR

Multi-Level IR Compiler Framework

'x86vector' Dialect

Operation definition 

x86vector.avx.intr.dp.ps.256 (::mlir::x86vector::DotIntrOp) 

Operands: 

OperandDescription
avector of 32-bit float values of length 8
bvector of 32-bit float values of length 8
c8-bit signless integer

Results: 

ResultDescription
resvector of 32-bit float values of length 8

x86vector.avx.intr.dot (::mlir::x86vector::DotOp) 

Dot

Syntax:

operation ::= `x86vector.avx.intr.dot` $a `,` $b attr-dict `:` type($res)

Computes the 4-way dot products of the lower and higher parts of the source vectors and broadcasts the two results to the lower and higher elements of the destination vector, respectively. Adding one element of the lower part to one element of the higher part in the destination vector yields the full dot product of the two source vectors.

Example:

%0 = x86vector.avx.intr.dot %a, %b : vector<8xf32>
%1 = vector.extractelement %0[%i0 : i32]: vector<8xf32>
%2 = vector.extractelement %0[%i4 : i32]: vector<8xf32>
%d = arith.addf %1, %2 : f32

Operands: 

OperandDescription
avector of 32-bit float values of length 8
bvector of 32-bit float values of length 8

Results: 

ResultDescription
resvector of 32-bit float values of length 8

x86vector.avx512.intr.mask.compress (::mlir::x86vector::MaskCompressIntrOp) 

Operands: 

OperandDescription
avector of 32-bit float or 32-bit signless integer or 64-bit float or 64-bit signless integer values of length 16/8
srcvector of 32-bit float or 32-bit signless integer or 64-bit float or 64-bit signless integer values of length 16/8
kvector of 1-bit signless integer values of length 16/8

Results: 

ResultDescription
resLLVM dialect-compatible type

x86vector.avx512.mask.compress (::mlir::x86vector::MaskCompressOp) 

Masked compress op

Syntax:

operation ::= `x86vector.avx512.mask.compress` $k `,` $a (`,` $src^)? attr-dict `:` type($dst) (`,` type($src)^)?

The mask.compress op is an AVX512 specific op that can lower to the llvm.mask.compress instruction. Instead of src, a constant vector vector attribute constant_src may be specified. If neither src nor constant_src is specified, the remaining elements in the result vector are set to zero.

From the Intel Intrinsics Guide: 

Contiguously store the active integer/floating-point elements in a (those with their respective bit set in writemask k) to dst, and pass through the remaining elements from src.

Attributes: 

AttributeMLIR TypeDescription
constant_src::mlir::ElementsAttrconstant vector/tensor attribute

Operands: 

OperandDescription
kvector of 1-bit signless integer values of length 16/8
avector of 32-bit float or 32-bit signless integer or 64-bit float or 64-bit signless integer values of length 16/8
srcvector of 32-bit float or 32-bit signless integer or 64-bit float or 64-bit signless integer values of length 16/8

Results: 

ResultDescription
dstvector of 32-bit float or 32-bit signless integer or 64-bit float or 64-bit signless integer values of length 16/8

x86vector.avx512.mask.rndscale (::mlir::x86vector::MaskRndScaleOp) 

Masked roundscale op

Syntax:

operation ::= `x86vector.avx512.mask.rndscale` $src `,` $k `,` $a `,` $imm `,` $rounding attr-dict `:` type($dst)

The mask.rndscale op is an AVX512 specific op that can lower to the proper LLVMAVX512 operation: llvm.mask.rndscale.ps.512 or llvm.mask.rndscale.pd.512 instruction depending on the type of vectors it is applied to.

From the Intel Intrinsics Guide: 

Round packed floating-point elements in a to the number of fraction bits specified by imm, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).

Operands: 

OperandDescription
srcvector of 32-bit float or 64-bit float values of length 16/8
k32-bit signless integer
avector of 32-bit float or 64-bit float values of length 16/8
imm16-bit signless integer or 8-bit signless integer
rounding32-bit signless integer

Results: 

ResultDescription
dstvector of 32-bit float or 64-bit float values of length 16/8

x86vector.avx512.intr.mask.rndscale.pd.512 (::mlir::x86vector::MaskRndScalePDIntrOp) 

Operands: 

OperandDescription
srcvector of 64-bit float values of length 8
k32-bit signless integer
avector of 64-bit float values of length 8
imm8-bit signless integer
roundingLLVM dialect-compatible type

Results: 

ResultDescription
resLLVM dialect-compatible type

x86vector.avx512.intr.mask.rndscale.ps.512 (::mlir::x86vector::MaskRndScalePSIntrOp) 

Operands: 

OperandDescription
srcvector of 32-bit float values of length 16
k32-bit signless integer
avector of 32-bit float values of length 16
imm16-bit signless integer
roundingLLVM dialect-compatible type

Results: 

ResultDescription
resLLVM dialect-compatible type

x86vector.avx512.mask.scalef (::mlir::x86vector::MaskScaleFOp) 

ScaleF op

Syntax:

operation ::= `x86vector.avx512.mask.scalef` $src `,` $a `,` $b `,` $k `,` $rounding attr-dict `:` type($dst)

The mask.scalef op is an AVX512 specific op that can lower to the proper LLVMAVX512 operation: llvm.mask.scalef.ps.512 or llvm.mask.scalef.pd.512 depending on the type of MLIR vectors it is applied to.

From the Intel Intrinsics Guide: 

Scale the packed floating-point elements in a using values from b, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).

Operands: 

OperandDescription
srcvector of 32-bit float or 64-bit float values of length 16/8
avector of 32-bit float or 64-bit float values of length 16/8
bvector of 32-bit float or 64-bit float values of length 16/8
k16-bit signless integer or 8-bit signless integer
rounding32-bit signless integer

Results: 

ResultDescription
dstvector of 32-bit float or 64-bit float values of length 16/8

x86vector.avx512.intr.mask.scalef.pd.512 (::mlir::x86vector::MaskScaleFPDIntrOp) 

Operands: 

OperandDescription
srcvector of 64-bit float values of length 8
avector of 64-bit float values of length 8
bvector of 64-bit float values of length 8
k8-bit signless integer
roundingLLVM dialect-compatible type

Results: 

ResultDescription
resLLVM dialect-compatible type

x86vector.avx512.intr.mask.scalef.ps.512 (::mlir::x86vector::MaskScaleFPSIntrOp) 

Operands: 

OperandDescription
srcvector of 32-bit float values of length 16
avector of 32-bit float values of length 16
bvector of 32-bit float values of length 16
k16-bit signless integer
roundingLLVM dialect-compatible type

Results: 

ResultDescription
resLLVM dialect-compatible type

x86vector.avx.intr.rsqrt.ps.256 (::mlir::x86vector::RsqrtIntrOp) 

Operands: 

OperandDescription
avector of 32-bit float values of length 8

Results: 

ResultDescription
resLLVM dialect-compatible type

x86vector.avx.rsqrt (::mlir::x86vector::RsqrtOp) 

Rsqrt

Syntax:

operation ::= `x86vector.avx.rsqrt` $a attr-dict `:` type($a)

Operands: 

OperandDescription
avector of 32-bit float values of length 8

Results: 

ResultDescription
bvector of 32-bit float values of length 8

x86vector.avx512.intr.vp2intersect.d.512 (::mlir::x86vector::Vp2IntersectDIntrOp) 

Operands: 

OperandDescription
avector of 32-bit signless integer values of length 16
bvector of 32-bit signless integer values of length 16

Results: 

ResultDescription
resLLVM dialect-compatible type

x86vector.avx512.vp2intersect (::mlir::x86vector::Vp2IntersectOp) 

Vp2Intersect op

Syntax:

operation ::= `x86vector.avx512.vp2intersect` $a `,` $b attr-dict `:` type($a)

The vp2intersect op is an AVX512 specific op that can lower to the proper LLVMAVX512 operation: llvm.vp2intersect.d.512 or llvm.vp2intersect.q.512 depending on the type of MLIR vectors it is applied to.

From the Intel Intrinsics Guide: 

Compute intersection of packed integer vectors a and b, and store indication of match in the corresponding bit of two mask registers specified by k1 and k2. A match in corresponding elements of a and b is indicated by a set bit in the corresponding bit of the mask registers.

Operands: 

OperandDescription
avector of 32-bit signless integer or 64-bit signless integer values of length 16/8
bvector of 32-bit signless integer or 64-bit signless integer values of length 16/8

Results: 

ResultDescription
k1vector of 1-bit signless integer values of length 16/8
k2vector of 1-bit signless integer values of length 16/8

x86vector.avx512.intr.vp2intersect.q.512 (::mlir::x86vector::Vp2IntersectQIntrOp) 

Operands: 

OperandDescription
avector of 64-bit signless integer values of length 8
bvector of 64-bit signless integer values of length 8

Results: 

ResultDescription
resLLVM dialect-compatible type