mlir.dialects.rocdl =================== .. py:module:: mlir.dialects.rocdl Classes ------- .. autoapisummary:: mlir.dialects.rocdl.ROCDLCos mlir.dialects.rocdl.ROCDLCosAdaptor mlir.dialects.rocdl.ROCDLExp mlir.dialects.rocdl.ROCDLExpAdaptor mlir.dialects.rocdl.ROCDLExp2 mlir.dialects.rocdl.ROCDLExp2Adaptor mlir.dialects.rocdl.ROCDLLog mlir.dialects.rocdl.ROCDLLogAdaptor mlir.dialects.rocdl.ROCDLRcp mlir.dialects.rocdl.ROCDLRcpAdaptor mlir.dialects.rocdl.ROCDLRsq mlir.dialects.rocdl.ROCDLRsqAdaptor mlir.dialects.rocdl.ROCDLSin mlir.dialects.rocdl.ROCDLSinAdaptor mlir.dialects.rocdl.ROCDLSqrt mlir.dialects.rocdl.ROCDLSqrtAdaptor mlir.dialects.rocdl.ROCDLTanh mlir.dialects.rocdl.ROCDLTanhAdaptor mlir.dialects.rocdl.AsyncmarkOp mlir.dialects.rocdl.AsyncmarkOpAdaptor mlir.dialects.rocdl.BallotOp mlir.dialects.rocdl.BallotOpAdaptor mlir.dialects.rocdl.BarrierInitOp mlir.dialects.rocdl.BarrierInitOpAdaptor mlir.dialects.rocdl.BarrierJoinOp mlir.dialects.rocdl.BarrierJoinOpAdaptor mlir.dialects.rocdl.BarrierLeaveOp mlir.dialects.rocdl.BarrierLeaveOpAdaptor mlir.dialects.rocdl.BarrierOp mlir.dialects.rocdl.BarrierOpAdaptor mlir.dialects.rocdl.BarrierSignalIsfirstOp mlir.dialects.rocdl.BarrierSignalIsfirstOpAdaptor mlir.dialects.rocdl.BarrierSignalOp mlir.dialects.rocdl.BarrierSignalOpAdaptor mlir.dialects.rocdl.BarrierSignalVarOp mlir.dialects.rocdl.BarrierSignalVarOpAdaptor mlir.dialects.rocdl.BarrierWaitOp mlir.dialects.rocdl.BarrierWaitOpAdaptor mlir.dialects.rocdl.BlockIdXOp mlir.dialects.rocdl.BlockIdXOpAdaptor mlir.dialects.rocdl.BlockIdYOp mlir.dialects.rocdl.BlockIdYOpAdaptor mlir.dialects.rocdl.BlockIdZOp mlir.dialects.rocdl.BlockIdZOpAdaptor mlir.dialects.rocdl.ClusterIdXOp mlir.dialects.rocdl.ClusterIdXOpAdaptor mlir.dialects.rocdl.ClusterIdYOp mlir.dialects.rocdl.ClusterIdYOpAdaptor mlir.dialects.rocdl.ClusterIdZOp mlir.dialects.rocdl.ClusterIdZOpAdaptor mlir.dialects.rocdl.ClusterLoadAsyncToLDSB8Op mlir.dialects.rocdl.ClusterLoadAsyncToLDSB8OpAdaptor mlir.dialects.rocdl.ClusterLoadAsyncToLDSB32Op mlir.dialects.rocdl.ClusterLoadAsyncToLDSB32OpAdaptor mlir.dialects.rocdl.ClusterLoadAsyncToLDSB64Op mlir.dialects.rocdl.ClusterLoadAsyncToLDSB64OpAdaptor mlir.dialects.rocdl.ClusterLoadAsyncToLDSB128Op mlir.dialects.rocdl.ClusterLoadAsyncToLDSB128OpAdaptor mlir.dialects.rocdl.ClusterWorkgroupIdXOp mlir.dialects.rocdl.ClusterWorkgroupIdXOpAdaptor mlir.dialects.rocdl.ClusterWorkgroupIdYOp mlir.dialects.rocdl.ClusterWorkgroupIdYOpAdaptor mlir.dialects.rocdl.ClusterWorkgroupIdZOp mlir.dialects.rocdl.ClusterWorkgroupIdZOpAdaptor mlir.dialects.rocdl.CvtF32Bf8Op mlir.dialects.rocdl.CvtF32Bf8OpAdaptor mlir.dialects.rocdl.CvtF32Fp8Op mlir.dialects.rocdl.CvtF32Fp8OpAdaptor mlir.dialects.rocdl.CvtPkBf8F32Op mlir.dialects.rocdl.CvtPkBf8F32OpAdaptor mlir.dialects.rocdl.CvtPkF32Bf8Op mlir.dialects.rocdl.CvtPkF32Bf8OpAdaptor mlir.dialects.rocdl.CvtPkF32Fp8Op mlir.dialects.rocdl.CvtPkF32Fp8OpAdaptor mlir.dialects.rocdl.CvtPkFp8F32Op mlir.dialects.rocdl.CvtPkFp8F32OpAdaptor mlir.dialects.rocdl.CvtPkRtz mlir.dialects.rocdl.CvtPkRtzAdaptor mlir.dialects.rocdl.CvtPkScalePk8Bf16Bf8Op mlir.dialects.rocdl.CvtPkScalePk8Bf16Bf8OpAdaptor mlir.dialects.rocdl.CvtPkScalePk8Bf16Fp4Op mlir.dialects.rocdl.CvtPkScalePk8Bf16Fp4OpAdaptor mlir.dialects.rocdl.CvtPkScalePk8Bf16Fp8Op mlir.dialects.rocdl.CvtPkScalePk8Bf16Fp8OpAdaptor mlir.dialects.rocdl.CvtPkScalePk8F16Bf8Op mlir.dialects.rocdl.CvtPkScalePk8F16Bf8OpAdaptor mlir.dialects.rocdl.CvtPkScalePk8F16Fp4Op mlir.dialects.rocdl.CvtPkScalePk8F16Fp4OpAdaptor mlir.dialects.rocdl.CvtPkScalePk8F16Fp8Op mlir.dialects.rocdl.CvtPkScalePk8F16Fp8OpAdaptor mlir.dialects.rocdl.CvtPkScalePk8F32Bf8Op mlir.dialects.rocdl.CvtPkScalePk8F32Bf8OpAdaptor mlir.dialects.rocdl.CvtPkScalePk8F32Fp4Op mlir.dialects.rocdl.CvtPkScalePk8F32Fp4OpAdaptor mlir.dialects.rocdl.CvtPkScalePk8F32Fp8Op mlir.dialects.rocdl.CvtPkScalePk8F32Fp8OpAdaptor mlir.dialects.rocdl.CvtPkScalePk16Bf16Bf6Op mlir.dialects.rocdl.CvtPkScalePk16Bf16Bf6OpAdaptor mlir.dialects.rocdl.CvtPkScalePk16Bf16Fp6Op mlir.dialects.rocdl.CvtPkScalePk16Bf16Fp6OpAdaptor mlir.dialects.rocdl.CvtPkScalePk16F16Bf6Op mlir.dialects.rocdl.CvtPkScalePk16F16Bf6OpAdaptor mlir.dialects.rocdl.CvtPkScalePk16F16Fp6Op mlir.dialects.rocdl.CvtPkScalePk16F16Fp6OpAdaptor mlir.dialects.rocdl.CvtPkScalePk16F32Bf6Op mlir.dialects.rocdl.CvtPkScalePk16F32Bf6OpAdaptor mlir.dialects.rocdl.CvtPkScalePk16F32Fp6Op mlir.dialects.rocdl.CvtPkScalePk16F32Fp6OpAdaptor mlir.dialects.rocdl.CvtScaleF32F16Bf8Op mlir.dialects.rocdl.CvtScaleF32F16Bf8OpAdaptor mlir.dialects.rocdl.CvtScaleF32F16Fp8Op mlir.dialects.rocdl.CvtScaleF32F16Fp8OpAdaptor mlir.dialects.rocdl.CvtScaleF32F32Bf8Op mlir.dialects.rocdl.CvtScaleF32F32Bf8OpAdaptor mlir.dialects.rocdl.CvtScaleF32F32Fp8Op mlir.dialects.rocdl.CvtScaleF32F32Fp8OpAdaptor mlir.dialects.rocdl.CvtScaleF32Pk8Bf8Bf16Op mlir.dialects.rocdl.CvtScaleF32Pk8Bf8Bf16OpAdaptor mlir.dialects.rocdl.CvtScaleF32Pk8Bf8F16Op mlir.dialects.rocdl.CvtScaleF32Pk8Bf8F16OpAdaptor mlir.dialects.rocdl.CvtScaleF32Pk8Bf8F32Op mlir.dialects.rocdl.CvtScaleF32Pk8Bf8F32OpAdaptor mlir.dialects.rocdl.CvtScaleF32Pk8Fp4Bf16Op mlir.dialects.rocdl.CvtScaleF32Pk8Fp4Bf16OpAdaptor mlir.dialects.rocdl.CvtScaleF32Pk8Fp4F16Op mlir.dialects.rocdl.CvtScaleF32Pk8Fp4F16OpAdaptor mlir.dialects.rocdl.CvtScaleF32Pk8Fp4F32Op mlir.dialects.rocdl.CvtScaleF32Pk8Fp4F32OpAdaptor mlir.dialects.rocdl.CvtScaleF32Pk8Fp8Bf16Op mlir.dialects.rocdl.CvtScaleF32Pk8Fp8Bf16OpAdaptor mlir.dialects.rocdl.CvtScaleF32Pk8Fp8F16Op mlir.dialects.rocdl.CvtScaleF32Pk8Fp8F16OpAdaptor mlir.dialects.rocdl.CvtScaleF32Pk8Fp8F32Op mlir.dialects.rocdl.CvtScaleF32Pk8Fp8F32OpAdaptor mlir.dialects.rocdl.CvtScaleF32Pk16Bf6Bf16Op mlir.dialects.rocdl.CvtScaleF32Pk16Bf6Bf16OpAdaptor mlir.dialects.rocdl.CvtScaleF32Pk16Bf6F16Op mlir.dialects.rocdl.CvtScaleF32Pk16Bf6F16OpAdaptor mlir.dialects.rocdl.CvtScaleF32Pk16Bf6F32Op mlir.dialects.rocdl.CvtScaleF32Pk16Bf6F32OpAdaptor mlir.dialects.rocdl.CvtScaleF32Pk16Fp6Bf16Op mlir.dialects.rocdl.CvtScaleF32Pk16Fp6Bf16OpAdaptor mlir.dialects.rocdl.CvtScaleF32Pk16Fp6F16Op mlir.dialects.rocdl.CvtScaleF32Pk16Fp6F16OpAdaptor mlir.dialects.rocdl.CvtScaleF32Pk16Fp6F32Op mlir.dialects.rocdl.CvtScaleF32Pk16Fp6F32OpAdaptor mlir.dialects.rocdl.CvtScaleF32Pk32Bf6Bf16Op mlir.dialects.rocdl.CvtScaleF32Pk32Bf6Bf16OpAdaptor mlir.dialects.rocdl.CvtScaleF32Pk32Bf6F16Op mlir.dialects.rocdl.CvtScaleF32Pk32Bf6F16OpAdaptor mlir.dialects.rocdl.CvtScaleF32Pk32Bf16Bf6Op mlir.dialects.rocdl.CvtScaleF32Pk32Bf16Bf6OpAdaptor mlir.dialects.rocdl.CvtScaleF32Pk32Bf16Fp6Op mlir.dialects.rocdl.CvtScaleF32Pk32Bf16Fp6OpAdaptor mlir.dialects.rocdl.CvtScaleF32Pk32F16Bf6Op mlir.dialects.rocdl.CvtScaleF32Pk32F16Bf6OpAdaptor mlir.dialects.rocdl.CvtScaleF32Pk32F16Fp6Op mlir.dialects.rocdl.CvtScaleF32Pk32F16Fp6OpAdaptor mlir.dialects.rocdl.CvtScaleF32Pk32F32Bf6Op mlir.dialects.rocdl.CvtScaleF32Pk32F32Bf6OpAdaptor mlir.dialects.rocdl.CvtScaleF32Pk32F32Fp6Op mlir.dialects.rocdl.CvtScaleF32Pk32F32Fp6OpAdaptor mlir.dialects.rocdl.CvtScaleF32Pk32Fp6Bf16Op mlir.dialects.rocdl.CvtScaleF32Pk32Fp6Bf16OpAdaptor mlir.dialects.rocdl.CvtScaleF32Pk32Fp6F16Op mlir.dialects.rocdl.CvtScaleF32Pk32Fp6F16OpAdaptor mlir.dialects.rocdl.CvtScaleF32PkBf8Bf16Op mlir.dialects.rocdl.CvtScaleF32PkBf8Bf16OpAdaptor mlir.dialects.rocdl.CvtScaleF32PkBf8F16Op mlir.dialects.rocdl.CvtScaleF32PkBf8F16OpAdaptor mlir.dialects.rocdl.CvtScaleF32PkBf8F32Op mlir.dialects.rocdl.CvtScaleF32PkBf8F32OpAdaptor mlir.dialects.rocdl.CvtScaleF32PkBf16Bf8Op mlir.dialects.rocdl.CvtScaleF32PkBf16Bf8OpAdaptor mlir.dialects.rocdl.CvtScaleF32PkBf16Fp4Op mlir.dialects.rocdl.CvtScaleF32PkBf16Fp4OpAdaptor mlir.dialects.rocdl.CvtScaleF32PkBf16Fp8Op mlir.dialects.rocdl.CvtScaleF32PkBf16Fp8OpAdaptor mlir.dialects.rocdl.CvtScaleF32PkF16Bf8Op mlir.dialects.rocdl.CvtScaleF32PkF16Bf8OpAdaptor mlir.dialects.rocdl.CvtScaleF32PkF16Fp4Op mlir.dialects.rocdl.CvtScaleF32PkF16Fp4OpAdaptor mlir.dialects.rocdl.CvtScaleF32PkF16Fp8Op mlir.dialects.rocdl.CvtScaleF32PkF16Fp8OpAdaptor mlir.dialects.rocdl.CvtScaleF32PkF32Bf8Op mlir.dialects.rocdl.CvtScaleF32PkF32Bf8OpAdaptor mlir.dialects.rocdl.CvtScaleF32PkF32Fp4Op mlir.dialects.rocdl.CvtScaleF32PkF32Fp4OpAdaptor mlir.dialects.rocdl.CvtScaleF32PkF32Fp8Op mlir.dialects.rocdl.CvtScaleF32PkF32Fp8OpAdaptor mlir.dialects.rocdl.CvtScaleF32PkFp4Bf16Op mlir.dialects.rocdl.CvtScaleF32PkFp4Bf16OpAdaptor mlir.dialects.rocdl.CvtScaleF32PkFp4F16Op mlir.dialects.rocdl.CvtScaleF32PkFp4F16OpAdaptor mlir.dialects.rocdl.CvtScaleF32PkFp4F32Op mlir.dialects.rocdl.CvtScaleF32PkFp4F32OpAdaptor mlir.dialects.rocdl.CvtScaleF32PkFp8Bf16Op mlir.dialects.rocdl.CvtScaleF32PkFp8Bf16OpAdaptor mlir.dialects.rocdl.CvtScaleF32PkFp8F16Op mlir.dialects.rocdl.CvtScaleF32PkFp8F16OpAdaptor mlir.dialects.rocdl.CvtScaleF32PkFp8F32Op mlir.dialects.rocdl.CvtScaleF32PkFp8F32OpAdaptor mlir.dialects.rocdl.CvtScaleF32SrBf8BF16Op mlir.dialects.rocdl.CvtScaleF32SrBf8BF16OpAdaptor mlir.dialects.rocdl.CvtScaleF32SrBf8F16Op mlir.dialects.rocdl.CvtScaleF32SrBf8F16OpAdaptor mlir.dialects.rocdl.CvtScaleF32SrBf8F32Op mlir.dialects.rocdl.CvtScaleF32SrBf8F32OpAdaptor mlir.dialects.rocdl.CvtScaleF32SrFp8BF16Op mlir.dialects.rocdl.CvtScaleF32SrFp8BF16OpAdaptor mlir.dialects.rocdl.CvtScaleF32SrFp8F16Op mlir.dialects.rocdl.CvtScaleF32SrFp8F16OpAdaptor mlir.dialects.rocdl.CvtScaleF32SrFp8F32Op mlir.dialects.rocdl.CvtScaleF32SrFp8F32OpAdaptor mlir.dialects.rocdl.CvtScaleF32SrPk8Bf8Bf16Op mlir.dialects.rocdl.CvtScaleF32SrPk8Bf8Bf16OpAdaptor mlir.dialects.rocdl.CvtScaleF32SrPk8Bf8F16Op mlir.dialects.rocdl.CvtScaleF32SrPk8Bf8F16OpAdaptor mlir.dialects.rocdl.CvtScaleF32SrPk8Bf8F32Op mlir.dialects.rocdl.CvtScaleF32SrPk8Bf8F32OpAdaptor mlir.dialects.rocdl.CvtScaleF32SrPk8Fp4Bf16Op mlir.dialects.rocdl.CvtScaleF32SrPk8Fp4Bf16OpAdaptor mlir.dialects.rocdl.CvtScaleF32SrPk8Fp4F16Op mlir.dialects.rocdl.CvtScaleF32SrPk8Fp4F16OpAdaptor mlir.dialects.rocdl.CvtScaleF32SrPk8Fp4F32Op mlir.dialects.rocdl.CvtScaleF32SrPk8Fp4F32OpAdaptor mlir.dialects.rocdl.CvtScaleF32SrPk8Fp8Bf16Op mlir.dialects.rocdl.CvtScaleF32SrPk8Fp8Bf16OpAdaptor mlir.dialects.rocdl.CvtScaleF32SrPk8Fp8F16Op mlir.dialects.rocdl.CvtScaleF32SrPk8Fp8F16OpAdaptor mlir.dialects.rocdl.CvtScaleF32SrPk8Fp8F32Op mlir.dialects.rocdl.CvtScaleF32SrPk8Fp8F32OpAdaptor mlir.dialects.rocdl.CvtScaleF32SrPk16Bf6Bf16Op mlir.dialects.rocdl.CvtScaleF32SrPk16Bf6Bf16OpAdaptor mlir.dialects.rocdl.CvtScaleF32SrPk16Bf6F16Op mlir.dialects.rocdl.CvtScaleF32SrPk16Bf6F16OpAdaptor mlir.dialects.rocdl.CvtScaleF32SrPk16Bf6F32Op mlir.dialects.rocdl.CvtScaleF32SrPk16Bf6F32OpAdaptor mlir.dialects.rocdl.CvtScaleF32SrPk16Fp6Bf16Op mlir.dialects.rocdl.CvtScaleF32SrPk16Fp6Bf16OpAdaptor mlir.dialects.rocdl.CvtScaleF32SrPk16Fp6F16Op mlir.dialects.rocdl.CvtScaleF32SrPk16Fp6F16OpAdaptor mlir.dialects.rocdl.CvtScaleF32SrPk16Fp6F32Op mlir.dialects.rocdl.CvtScaleF32SrPk16Fp6F32OpAdaptor mlir.dialects.rocdl.CvtScaleF32SrPk32Bf6Bf16Op mlir.dialects.rocdl.CvtScaleF32SrPk32Bf6Bf16OpAdaptor mlir.dialects.rocdl.CvtScaleF32SrPk32Bf6F16Op mlir.dialects.rocdl.CvtScaleF32SrPk32Bf6F16OpAdaptor mlir.dialects.rocdl.CvtScaleF32SrPk32Bf6F32Op mlir.dialects.rocdl.CvtScaleF32SrPk32Bf6F32OpAdaptor mlir.dialects.rocdl.CvtScaleF32SrPk32Fp6Bf16Op mlir.dialects.rocdl.CvtScaleF32SrPk32Fp6Bf16OpAdaptor mlir.dialects.rocdl.CvtScaleF32SrPk32Fp6F16Op mlir.dialects.rocdl.CvtScaleF32SrPk32Fp6F16OpAdaptor mlir.dialects.rocdl.CvtScaleF32SrPk32Fp6F32Op mlir.dialects.rocdl.CvtScaleF32SrPk32Fp6F32OpAdaptor mlir.dialects.rocdl.CvtScaleF32SrPkFp4Bf16Op mlir.dialects.rocdl.CvtScaleF32SrPkFp4Bf16OpAdaptor mlir.dialects.rocdl.CvtScaleF32SrPkFp4F16Op mlir.dialects.rocdl.CvtScaleF32SrPkFp4F16OpAdaptor mlir.dialects.rocdl.CvtScaleF32SrPkFp4F32Op mlir.dialects.rocdl.CvtScaleF32SrPkFp4F32OpAdaptor mlir.dialects.rocdl.CvtScaleF322xPk16Bf6F32Op mlir.dialects.rocdl.CvtScaleF322xPk16Bf6F32OpAdaptor mlir.dialects.rocdl.CvtScaleF322xPk16Fp6F32Op mlir.dialects.rocdl.CvtScaleF322xPk16Fp6F32OpAdaptor mlir.dialects.rocdl.CvtSrBf8F32Op mlir.dialects.rocdl.CvtSrBf8F32OpAdaptor mlir.dialects.rocdl.CvtSrFp8F32Op mlir.dialects.rocdl.CvtSrFp8F32OpAdaptor mlir.dialects.rocdl.DPPUpdateOp mlir.dialects.rocdl.DPPUpdateOpAdaptor mlir.dialects.rocdl.DsAtomicAsyncBarrierArriveOp mlir.dialects.rocdl.DsAtomicAsyncBarrierArriveOpAdaptor mlir.dialects.rocdl.DsAtomicBarrierArriveRtnOp mlir.dialects.rocdl.DsAtomicBarrierArriveRtnOpAdaptor mlir.dialects.rocdl.DsBpermuteOp mlir.dialects.rocdl.DsBpermuteOpAdaptor mlir.dialects.rocdl.DsLoadTr4_B64 mlir.dialects.rocdl.DsLoadTr4_B64Adaptor mlir.dialects.rocdl.DsLoadTr6_B96 mlir.dialects.rocdl.DsLoadTr6_B96Adaptor mlir.dialects.rocdl.DsLoadTr8_B64 mlir.dialects.rocdl.DsLoadTr8_B64Adaptor mlir.dialects.rocdl.DsLoadTr16_B128 mlir.dialects.rocdl.DsLoadTr16_B128Adaptor mlir.dialects.rocdl.DsSwizzleOp mlir.dialects.rocdl.DsSwizzleOpAdaptor mlir.dialects.rocdl.FMed3Op mlir.dialects.rocdl.FMed3OpAdaptor mlir.dialects.rocdl.FlatPrefetchOp mlir.dialects.rocdl.FlatPrefetchOpAdaptor mlir.dialects.rocdl.GetBarrierStateOp mlir.dialects.rocdl.GetBarrierStateOpAdaptor mlir.dialects.rocdl.GetNamedBarrierStateOp mlir.dialects.rocdl.GetNamedBarrierStateOpAdaptor mlir.dialects.rocdl.GlobalLoadAsyncLDSOp mlir.dialects.rocdl.GlobalLoadAsyncLDSOpAdaptor mlir.dialects.rocdl.GlobalLoadAsyncToLDSB8Op mlir.dialects.rocdl.GlobalLoadAsyncToLDSB8OpAdaptor mlir.dialects.rocdl.GlobalLoadAsyncToLDSB32Op mlir.dialects.rocdl.GlobalLoadAsyncToLDSB32OpAdaptor mlir.dialects.rocdl.GlobalLoadAsyncToLDSB64Op mlir.dialects.rocdl.GlobalLoadAsyncToLDSB64OpAdaptor mlir.dialects.rocdl.GlobalLoadAsyncToLDSB128Op mlir.dialects.rocdl.GlobalLoadAsyncToLDSB128OpAdaptor mlir.dialects.rocdl.GlobalLoadLDSOp mlir.dialects.rocdl.GlobalLoadLDSOpAdaptor mlir.dialects.rocdl.GlobalLoadTr4_B64 mlir.dialects.rocdl.GlobalLoadTr4_B64Adaptor mlir.dialects.rocdl.GlobalLoadTr6_B96 mlir.dialects.rocdl.GlobalLoadTr6_B96Adaptor mlir.dialects.rocdl.GlobalLoadTr8_B64 mlir.dialects.rocdl.GlobalLoadTr8_B64Adaptor mlir.dialects.rocdl.GlobalLoadTr8_B128 mlir.dialects.rocdl.GlobalLoadTr8_B128Adaptor mlir.dialects.rocdl.GlobalPrefetchOp mlir.dialects.rocdl.GlobalPrefetchOpAdaptor mlir.dialects.rocdl.GlobalStoreAsyncFromLDSB8Op mlir.dialects.rocdl.GlobalStoreAsyncFromLDSB8OpAdaptor mlir.dialects.rocdl.GlobalStoreAsyncFromLDSB32Op mlir.dialects.rocdl.GlobalStoreAsyncFromLDSB32OpAdaptor mlir.dialects.rocdl.GlobalStoreAsyncFromLDSB64Op mlir.dialects.rocdl.GlobalStoreAsyncFromLDSB64OpAdaptor mlir.dialects.rocdl.GlobalStoreAsyncFromLDSB128Op mlir.dialects.rocdl.GlobalStoreAsyncFromLDSB128OpAdaptor mlir.dialects.rocdl.IglpOpt mlir.dialects.rocdl.IglpOptAdaptor mlir.dialects.rocdl.LoadAsyncToLDSOp mlir.dialects.rocdl.LoadAsyncToLDSOpAdaptor mlir.dialects.rocdl.LoadToLDSOp mlir.dialects.rocdl.LoadToLDSOpAdaptor mlir.dialects.rocdl.MakeBufferRsrcOp mlir.dialects.rocdl.MakeBufferRsrcOpAdaptor mlir.dialects.rocdl.MbcntHiOp mlir.dialects.rocdl.MbcntHiOpAdaptor mlir.dialects.rocdl.MbcntLoOp mlir.dialects.rocdl.MbcntLoOpAdaptor mlir.dialects.rocdl.Permlane16SwapOp mlir.dialects.rocdl.Permlane16SwapOpAdaptor mlir.dialects.rocdl.Permlane16VarOp mlir.dialects.rocdl.Permlane16VarOpAdaptor mlir.dialects.rocdl.Permlane32SwapOp mlir.dialects.rocdl.Permlane32SwapOpAdaptor mlir.dialects.rocdl.PermlaneX16Op mlir.dialects.rocdl.PermlaneX16OpAdaptor mlir.dialects.rocdl.PermlaneX16VarOp mlir.dialects.rocdl.PermlaneX16VarOpAdaptor mlir.dialects.rocdl.PtrSBufferLoadOp mlir.dialects.rocdl.PtrSBufferLoadOpAdaptor mlir.dialects.rocdl.RawBufferAtomicCmpSwap mlir.dialects.rocdl.RawBufferAtomicCmpSwapAdaptor mlir.dialects.rocdl.RawBufferAtomicFAddOp mlir.dialects.rocdl.RawBufferAtomicFAddOpAdaptor mlir.dialects.rocdl.RawBufferAtomicFMaxOp mlir.dialects.rocdl.RawBufferAtomicFMaxOpAdaptor mlir.dialects.rocdl.RawBufferAtomicSMaxOp mlir.dialects.rocdl.RawBufferAtomicSMaxOpAdaptor mlir.dialects.rocdl.RawBufferAtomicUMinOp mlir.dialects.rocdl.RawBufferAtomicUMinOpAdaptor mlir.dialects.rocdl.RawBufferLoadOp mlir.dialects.rocdl.RawBufferLoadOpAdaptor mlir.dialects.rocdl.RawBufferStoreOp mlir.dialects.rocdl.RawBufferStoreOpAdaptor mlir.dialects.rocdl.RawPtrBufferAtomicCmpSwap mlir.dialects.rocdl.RawPtrBufferAtomicCmpSwapAdaptor mlir.dialects.rocdl.RawPtrBufferAtomicFaddOp mlir.dialects.rocdl.RawPtrBufferAtomicFaddOpAdaptor mlir.dialects.rocdl.RawPtrBufferAtomicFmaxOp mlir.dialects.rocdl.RawPtrBufferAtomicFmaxOpAdaptor mlir.dialects.rocdl.RawPtrBufferAtomicSmaxOp mlir.dialects.rocdl.RawPtrBufferAtomicSmaxOpAdaptor mlir.dialects.rocdl.RawPtrBufferAtomicUminOp mlir.dialects.rocdl.RawPtrBufferAtomicUminOpAdaptor mlir.dialects.rocdl.RawPtrBufferLoadAsyncLdsOp mlir.dialects.rocdl.RawPtrBufferLoadAsyncLdsOpAdaptor mlir.dialects.rocdl.RawPtrBufferLoadLdsOp mlir.dialects.rocdl.RawPtrBufferLoadLdsOpAdaptor mlir.dialects.rocdl.RawPtrBufferLoadOp mlir.dialects.rocdl.RawPtrBufferLoadOpAdaptor mlir.dialects.rocdl.RawPtrBufferStoreOp mlir.dialects.rocdl.RawPtrBufferStoreOpAdaptor mlir.dialects.rocdl.ReadfirstlaneOp mlir.dialects.rocdl.ReadfirstlaneOpAdaptor mlir.dialects.rocdl.ReadlaneOp mlir.dialects.rocdl.ReadlaneOpAdaptor mlir.dialects.rocdl.SBarrierOp mlir.dialects.rocdl.SBarrierOpAdaptor mlir.dialects.rocdl.SNopOp mlir.dialects.rocdl.SNopOpAdaptor mlir.dialects.rocdl.SSleepOp mlir.dialects.rocdl.SSleepOpAdaptor mlir.dialects.rocdl.SWaitcntOp mlir.dialects.rocdl.SWaitcntOpAdaptor mlir.dialects.rocdl.SchedBarrier mlir.dialects.rocdl.SchedBarrierAdaptor mlir.dialects.rocdl.SchedGroupBarrier mlir.dialects.rocdl.SchedGroupBarrierAdaptor mlir.dialects.rocdl.SetPrioOp mlir.dialects.rocdl.SetPrioOpAdaptor mlir.dialects.rocdl.TensorLoadToLDSOp mlir.dialects.rocdl.TensorLoadToLDSOpAdaptor mlir.dialects.rocdl.TensorStoreFromLDSOp mlir.dialects.rocdl.TensorStoreFromLDSOpAdaptor mlir.dialects.rocdl.ThreadIdXOp mlir.dialects.rocdl.ThreadIdXOpAdaptor mlir.dialects.rocdl.ThreadIdYOp mlir.dialects.rocdl.ThreadIdYOpAdaptor mlir.dialects.rocdl.ThreadIdZOp mlir.dialects.rocdl.ThreadIdZOpAdaptor mlir.dialects.rocdl.WaitAsynccntOp mlir.dialects.rocdl.WaitAsynccntOpAdaptor mlir.dialects.rocdl.WaitAsyncmarkOp mlir.dialects.rocdl.WaitAsyncmarkOpAdaptor mlir.dialects.rocdl.WaitDscntOp mlir.dialects.rocdl.WaitDscntOpAdaptor mlir.dialects.rocdl.WaitExpcntOp mlir.dialects.rocdl.WaitExpcntOpAdaptor mlir.dialects.rocdl.WaitLoadcntOp mlir.dialects.rocdl.WaitLoadcntOpAdaptor mlir.dialects.rocdl.WaitStorecntOp mlir.dialects.rocdl.WaitStorecntOpAdaptor mlir.dialects.rocdl.WaitTensorcntOp mlir.dialects.rocdl.WaitTensorcntOpAdaptor mlir.dialects.rocdl.WakeupBarrierOp mlir.dialects.rocdl.WakeupBarrierOpAdaptor mlir.dialects.rocdl.WaveBarrierOp mlir.dialects.rocdl.WaveBarrierOpAdaptor mlir.dialects.rocdl.WaveId mlir.dialects.rocdl.WaveIdAdaptor mlir.dialects.rocdl.WavefrontSizeOp mlir.dialects.rocdl.WavefrontSizeOpAdaptor mlir.dialects.rocdl.dot4_f32_bf8_bf8 mlir.dialects.rocdl.dot4_f32_bf8_bf8Adaptor mlir.dialects.rocdl.dot4_f32_bf8_fp8 mlir.dialects.rocdl.dot4_f32_bf8_fp8Adaptor mlir.dialects.rocdl.dot4_f32_fp8_bf8 mlir.dialects.rocdl.dot4_f32_fp8_bf8Adaptor mlir.dialects.rocdl.dot4_f32_fp8_fp8 mlir.dialects.rocdl.dot4_f32_fp8_fp8Adaptor mlir.dialects.rocdl.ds_read_tr4_b64 mlir.dialects.rocdl.ds_read_tr4_b64Adaptor mlir.dialects.rocdl.ds_read_tr6_b96 mlir.dialects.rocdl.ds_read_tr6_b96Adaptor mlir.dialects.rocdl.ds_read_tr8_b64 mlir.dialects.rocdl.ds_read_tr8_b64Adaptor mlir.dialects.rocdl.ds_read_tr16_b64 mlir.dialects.rocdl.ds_read_tr16_b64Adaptor mlir.dialects.rocdl.fdot2 mlir.dialects.rocdl.fdot2Adaptor mlir.dialects.rocdl.fdot2_bf16_bf16 mlir.dialects.rocdl.fdot2_bf16_bf16Adaptor mlir.dialects.rocdl.fdot2_f16_f16 mlir.dialects.rocdl.fdot2_f16_f16Adaptor mlir.dialects.rocdl.fdot2_f32_bf16 mlir.dialects.rocdl.fdot2_f32_bf16Adaptor mlir.dialects.rocdl.mfma_f32_4x4x1f32 mlir.dialects.rocdl.mfma_f32_4x4x1f32Adaptor mlir.dialects.rocdl.mfma_f32_4x4x2bf16 mlir.dialects.rocdl.mfma_f32_4x4x2bf16Adaptor mlir.dialects.rocdl.mfma_f32_4x4x4bf16_1k mlir.dialects.rocdl.mfma_f32_4x4x4bf16_1kAdaptor mlir.dialects.rocdl.mfma_f32_4x4x4f16 mlir.dialects.rocdl.mfma_f32_4x4x4f16Adaptor mlir.dialects.rocdl.mfma_f32_16x16x1f32 mlir.dialects.rocdl.mfma_f32_16x16x1f32Adaptor mlir.dialects.rocdl.mfma_f32_16x16x2bf16 mlir.dialects.rocdl.mfma_f32_16x16x2bf16Adaptor mlir.dialects.rocdl.mfma_f32_16x16x4bf16_1k mlir.dialects.rocdl.mfma_f32_16x16x4bf16_1kAdaptor mlir.dialects.rocdl.mfma_f32_16x16x4f16 mlir.dialects.rocdl.mfma_f32_16x16x4f16Adaptor mlir.dialects.rocdl.mfma_f32_16x16x4f32 mlir.dialects.rocdl.mfma_f32_16x16x4f32Adaptor mlir.dialects.rocdl.mfma_f32_16x16x8_xf32 mlir.dialects.rocdl.mfma_f32_16x16x8_xf32Adaptor mlir.dialects.rocdl.mfma_f32_16x16x8bf16 mlir.dialects.rocdl.mfma_f32_16x16x8bf16Adaptor mlir.dialects.rocdl.mfma_f32_16x16x16bf16_1k mlir.dialects.rocdl.mfma_f32_16x16x16bf16_1kAdaptor mlir.dialects.rocdl.mfma_f32_16x16x16f16 mlir.dialects.rocdl.mfma_f32_16x16x16f16Adaptor mlir.dialects.rocdl.mfma_f32_16x16x32_bf8_bf8 mlir.dialects.rocdl.mfma_f32_16x16x32_bf8_bf8Adaptor mlir.dialects.rocdl.mfma_f32_16x16x32_bf8_fp8 mlir.dialects.rocdl.mfma_f32_16x16x32_bf8_fp8Adaptor mlir.dialects.rocdl.mfma_f32_16x16x32_bf16 mlir.dialects.rocdl.mfma_f32_16x16x32_bf16Adaptor mlir.dialects.rocdl.mfma_f32_16x16x32_f16 mlir.dialects.rocdl.mfma_f32_16x16x32_f16Adaptor mlir.dialects.rocdl.mfma_f32_16x16x32_fp8_bf8 mlir.dialects.rocdl.mfma_f32_16x16x32_fp8_bf8Adaptor mlir.dialects.rocdl.mfma_f32_16x16x32_fp8_fp8 mlir.dialects.rocdl.mfma_f32_16x16x32_fp8_fp8Adaptor mlir.dialects.rocdl.mfma_f32_32x32x1f32 mlir.dialects.rocdl.mfma_f32_32x32x1f32Adaptor mlir.dialects.rocdl.mfma_f32_32x32x2bf16 mlir.dialects.rocdl.mfma_f32_32x32x2bf16Adaptor mlir.dialects.rocdl.mfma_f32_32x32x2f32 mlir.dialects.rocdl.mfma_f32_32x32x2f32Adaptor mlir.dialects.rocdl.mfma_f32_32x32x4_xf32 mlir.dialects.rocdl.mfma_f32_32x32x4_xf32Adaptor mlir.dialects.rocdl.mfma_f32_32x32x4bf16 mlir.dialects.rocdl.mfma_f32_32x32x4bf16Adaptor mlir.dialects.rocdl.mfma_f32_32x32x4bf16_1k mlir.dialects.rocdl.mfma_f32_32x32x4bf16_1kAdaptor mlir.dialects.rocdl.mfma_f32_32x32x4f16 mlir.dialects.rocdl.mfma_f32_32x32x4f16Adaptor mlir.dialects.rocdl.mfma_f32_32x32x8bf16_1k mlir.dialects.rocdl.mfma_f32_32x32x8bf16_1kAdaptor mlir.dialects.rocdl.mfma_f32_32x32x8f16 mlir.dialects.rocdl.mfma_f32_32x32x8f16Adaptor mlir.dialects.rocdl.mfma_f32_32x32x16_bf8_bf8 mlir.dialects.rocdl.mfma_f32_32x32x16_bf8_bf8Adaptor mlir.dialects.rocdl.mfma_f32_32x32x16_bf8_fp8 mlir.dialects.rocdl.mfma_f32_32x32x16_bf8_fp8Adaptor mlir.dialects.rocdl.mfma_f32_32x32x16_bf16 mlir.dialects.rocdl.mfma_f32_32x32x16_bf16Adaptor mlir.dialects.rocdl.mfma_f32_32x32x16_f16 mlir.dialects.rocdl.mfma_f32_32x32x16_f16Adaptor mlir.dialects.rocdl.mfma_f32_32x32x16_fp8_bf8 mlir.dialects.rocdl.mfma_f32_32x32x16_fp8_bf8Adaptor mlir.dialects.rocdl.mfma_f32_32x32x16_fp8_fp8 mlir.dialects.rocdl.mfma_f32_32x32x16_fp8_fp8Adaptor mlir.dialects.rocdl.mfma_f64_4x4x4f64 mlir.dialects.rocdl.mfma_f64_4x4x4f64Adaptor mlir.dialects.rocdl.mfma_f64_16x16x4f64 mlir.dialects.rocdl.mfma_f64_16x16x4f64Adaptor mlir.dialects.rocdl.mfma_i32_4x4x4i8 mlir.dialects.rocdl.mfma_i32_4x4x4i8Adaptor mlir.dialects.rocdl.mfma_i32_16x16x4i8 mlir.dialects.rocdl.mfma_i32_16x16x4i8Adaptor mlir.dialects.rocdl.mfma_i32_16x16x16i8 mlir.dialects.rocdl.mfma_i32_16x16x16i8Adaptor mlir.dialects.rocdl.mfma_i32_16x16x32_i8 mlir.dialects.rocdl.mfma_i32_16x16x32_i8Adaptor mlir.dialects.rocdl.mfma_i32_16x16x64_i8 mlir.dialects.rocdl.mfma_i32_16x16x64_i8Adaptor mlir.dialects.rocdl.mfma_i32_32x32x4i8 mlir.dialects.rocdl.mfma_i32_32x32x4i8Adaptor mlir.dialects.rocdl.mfma_i32_32x32x8i8 mlir.dialects.rocdl.mfma_i32_32x32x8i8Adaptor mlir.dialects.rocdl.mfma_i32_32x32x16_i8 mlir.dialects.rocdl.mfma_i32_32x32x16_i8Adaptor mlir.dialects.rocdl.mfma_i32_32x32x32_i8 mlir.dialects.rocdl.mfma_i32_32x32x32_i8Adaptor mlir.dialects.rocdl.mfma_scale_f32_16x16x128_f8f6f4 mlir.dialects.rocdl.mfma_scale_f32_16x16x128_f8f6f4Adaptor mlir.dialects.rocdl.mfma_scale_f32_32x32x64_f8f6f4 mlir.dialects.rocdl.mfma_scale_f32_32x32x64_f8f6f4Adaptor mlir.dialects.rocdl.sdot2 mlir.dialects.rocdl.sdot2Adaptor mlir.dialects.rocdl.sdot4 mlir.dialects.rocdl.sdot4Adaptor mlir.dialects.rocdl.sdot8 mlir.dialects.rocdl.sdot8Adaptor mlir.dialects.rocdl.smfmac_f32_16x16x32_bf16 mlir.dialects.rocdl.smfmac_f32_16x16x32_bf16Adaptor mlir.dialects.rocdl.smfmac_f32_16x16x32_f16 mlir.dialects.rocdl.smfmac_f32_16x16x32_f16Adaptor mlir.dialects.rocdl.smfmac_f32_16x16x64_bf8_bf8 mlir.dialects.rocdl.smfmac_f32_16x16x64_bf8_bf8Adaptor mlir.dialects.rocdl.smfmac_f32_16x16x64_bf8_fp8 mlir.dialects.rocdl.smfmac_f32_16x16x64_bf8_fp8Adaptor mlir.dialects.rocdl.smfmac_f32_16x16x64_bf16 mlir.dialects.rocdl.smfmac_f32_16x16x64_bf16Adaptor mlir.dialects.rocdl.smfmac_f32_16x16x64_f16 mlir.dialects.rocdl.smfmac_f32_16x16x64_f16Adaptor mlir.dialects.rocdl.smfmac_f32_16x16x64_fp8_bf8 mlir.dialects.rocdl.smfmac_f32_16x16x64_fp8_bf8Adaptor mlir.dialects.rocdl.smfmac_f32_16x16x64_fp8_fp8 mlir.dialects.rocdl.smfmac_f32_16x16x64_fp8_fp8Adaptor mlir.dialects.rocdl.smfmac_f32_16x16x128_bf8_bf8 mlir.dialects.rocdl.smfmac_f32_16x16x128_bf8_bf8Adaptor mlir.dialects.rocdl.smfmac_f32_16x16x128_bf8_fp8 mlir.dialects.rocdl.smfmac_f32_16x16x128_bf8_fp8Adaptor mlir.dialects.rocdl.smfmac_f32_16x16x128_fp8_bf8 mlir.dialects.rocdl.smfmac_f32_16x16x128_fp8_bf8Adaptor mlir.dialects.rocdl.smfmac_f32_16x16x128_fp8_fp8 mlir.dialects.rocdl.smfmac_f32_16x16x128_fp8_fp8Adaptor mlir.dialects.rocdl.smfmac_f32_32x32x16_bf16 mlir.dialects.rocdl.smfmac_f32_32x32x16_bf16Adaptor mlir.dialects.rocdl.smfmac_f32_32x32x16_f16 mlir.dialects.rocdl.smfmac_f32_32x32x16_f16Adaptor mlir.dialects.rocdl.smfmac_f32_32x32x32_bf8_bf8 mlir.dialects.rocdl.smfmac_f32_32x32x32_bf8_bf8Adaptor mlir.dialects.rocdl.smfmac_f32_32x32x32_bf8_fp8 mlir.dialects.rocdl.smfmac_f32_32x32x32_bf8_fp8Adaptor mlir.dialects.rocdl.smfmac_f32_32x32x32_bf16 mlir.dialects.rocdl.smfmac_f32_32x32x32_bf16Adaptor mlir.dialects.rocdl.smfmac_f32_32x32x32_f16 mlir.dialects.rocdl.smfmac_f32_32x32x32_f16Adaptor mlir.dialects.rocdl.smfmac_f32_32x32x32_fp8_bf8 mlir.dialects.rocdl.smfmac_f32_32x32x32_fp8_bf8Adaptor mlir.dialects.rocdl.smfmac_f32_32x32x32_fp8_fp8 mlir.dialects.rocdl.smfmac_f32_32x32x32_fp8_fp8Adaptor mlir.dialects.rocdl.smfmac_f32_32x32x64_bf8_bf8 mlir.dialects.rocdl.smfmac_f32_32x32x64_bf8_bf8Adaptor mlir.dialects.rocdl.smfmac_f32_32x32x64_bf8_fp8 mlir.dialects.rocdl.smfmac_f32_32x32x64_bf8_fp8Adaptor mlir.dialects.rocdl.smfmac_f32_32x32x64_fp8_bf8 mlir.dialects.rocdl.smfmac_f32_32x32x64_fp8_bf8Adaptor mlir.dialects.rocdl.smfmac_f32_32x32x64_fp8_fp8 mlir.dialects.rocdl.smfmac_f32_32x32x64_fp8_fp8Adaptor mlir.dialects.rocdl.smfmac_i32_16x16x64_i8 mlir.dialects.rocdl.smfmac_i32_16x16x64_i8Adaptor mlir.dialects.rocdl.smfmac_i32_16x16x128_i8 mlir.dialects.rocdl.smfmac_i32_16x16x128_i8Adaptor mlir.dialects.rocdl.smfmac_i32_32x32x32_i8 mlir.dialects.rocdl.smfmac_i32_32x32x32_i8Adaptor mlir.dialects.rocdl.smfmac_i32_32x32x64_i8 mlir.dialects.rocdl.smfmac_i32_32x32x64_i8Adaptor mlir.dialects.rocdl.sudot4 mlir.dialects.rocdl.sudot4Adaptor mlir.dialects.rocdl.sudot8 mlir.dialects.rocdl.sudot8Adaptor mlir.dialects.rocdl.swmmac_bf16_16x16x32_bf16 mlir.dialects.rocdl.swmmac_bf16_16x16x32_bf16Adaptor mlir.dialects.rocdl.swmmac_bf16_16x16x64_bf16 mlir.dialects.rocdl.swmmac_bf16_16x16x64_bf16Adaptor mlir.dialects.rocdl.swmmac_bf16f32_16x16x64_bf16 mlir.dialects.rocdl.swmmac_bf16f32_16x16x64_bf16Adaptor mlir.dialects.rocdl.swmmac_f16_16x16x32_f16 mlir.dialects.rocdl.swmmac_f16_16x16x32_f16Adaptor mlir.dialects.rocdl.swmmac_f16_16x16x64_f16 mlir.dialects.rocdl.swmmac_f16_16x16x64_f16Adaptor mlir.dialects.rocdl.swmmac_f16_16x16x128_bf8_bf8 mlir.dialects.rocdl.swmmac_f16_16x16x128_bf8_bf8Adaptor mlir.dialects.rocdl.swmmac_f16_16x16x128_bf8_fp8 mlir.dialects.rocdl.swmmac_f16_16x16x128_bf8_fp8Adaptor mlir.dialects.rocdl.swmmac_f16_16x16x128_fp8_bf8 mlir.dialects.rocdl.swmmac_f16_16x16x128_fp8_bf8Adaptor mlir.dialects.rocdl.swmmac_f16_16x16x128_fp8_fp8 mlir.dialects.rocdl.swmmac_f16_16x16x128_fp8_fp8Adaptor mlir.dialects.rocdl.swmmac_f32_16x16x32_bf8_bf8 mlir.dialects.rocdl.swmmac_f32_16x16x32_bf8_bf8Adaptor mlir.dialects.rocdl.swmmac_f32_16x16x32_bf8_fp8 mlir.dialects.rocdl.swmmac_f32_16x16x32_bf8_fp8Adaptor mlir.dialects.rocdl.swmmac_f32_16x16x32_bf16 mlir.dialects.rocdl.swmmac_f32_16x16x32_bf16Adaptor mlir.dialects.rocdl.swmmac_f32_16x16x32_f16 mlir.dialects.rocdl.swmmac_f32_16x16x32_f16Adaptor mlir.dialects.rocdl.swmmac_f32_16x16x32_fp8_bf8 mlir.dialects.rocdl.swmmac_f32_16x16x32_fp8_bf8Adaptor mlir.dialects.rocdl.swmmac_f32_16x16x32_fp8_fp8 mlir.dialects.rocdl.swmmac_f32_16x16x32_fp8_fp8Adaptor mlir.dialects.rocdl.swmmac_f32_16x16x64_bf16 mlir.dialects.rocdl.swmmac_f32_16x16x64_bf16Adaptor mlir.dialects.rocdl.swmmac_f32_16x16x64_f16 mlir.dialects.rocdl.swmmac_f32_16x16x64_f16Adaptor mlir.dialects.rocdl.swmmac_f32_16x16x128_bf8_bf8 mlir.dialects.rocdl.swmmac_f32_16x16x128_bf8_bf8Adaptor mlir.dialects.rocdl.swmmac_f32_16x16x128_bf8_fp8 mlir.dialects.rocdl.swmmac_f32_16x16x128_bf8_fp8Adaptor mlir.dialects.rocdl.swmmac_f32_16x16x128_fp8_bf8 mlir.dialects.rocdl.swmmac_f32_16x16x128_fp8_bf8Adaptor mlir.dialects.rocdl.swmmac_f32_16x16x128_fp8_fp8 mlir.dialects.rocdl.swmmac_f32_16x16x128_fp8_fp8Adaptor mlir.dialects.rocdl.swmmac_i32_16x16x32_iu4 mlir.dialects.rocdl.swmmac_i32_16x16x32_iu4Adaptor mlir.dialects.rocdl.swmmac_i32_16x16x32_iu8 mlir.dialects.rocdl.swmmac_i32_16x16x32_iu8Adaptor mlir.dialects.rocdl.swmmac_i32_16x16x64_iu4 mlir.dialects.rocdl.swmmac_i32_16x16x64_iu4Adaptor mlir.dialects.rocdl.swmmac_i32_16x16x128_iu8 mlir.dialects.rocdl.swmmac_i32_16x16x128_iu8Adaptor mlir.dialects.rocdl.udot2 mlir.dialects.rocdl.udot2Adaptor mlir.dialects.rocdl.udot4 mlir.dialects.rocdl.udot4Adaptor mlir.dialects.rocdl.udot8 mlir.dialects.rocdl.udot8Adaptor mlir.dialects.rocdl.wmma_bf16_16x16x16_bf16 mlir.dialects.rocdl.wmma_bf16_16x16x16_bf16Adaptor mlir.dialects.rocdl.wmma_bf16_16x16x32_bf16 mlir.dialects.rocdl.wmma_bf16_16x16x32_bf16Adaptor mlir.dialects.rocdl.wmma_bf16f32_16x16x32_bf16 mlir.dialects.rocdl.wmma_bf16f32_16x16x32_bf16Adaptor mlir.dialects.rocdl.wmma_f16_16x16x16_f16 mlir.dialects.rocdl.wmma_f16_16x16x16_f16Adaptor mlir.dialects.rocdl.wmma_f16_16x16x32_f16 mlir.dialects.rocdl.wmma_f16_16x16x32_f16Adaptor mlir.dialects.rocdl.wmma_f16_16x16x64_bf8_bf8 mlir.dialects.rocdl.wmma_f16_16x16x64_bf8_bf8Adaptor mlir.dialects.rocdl.wmma_f16_16x16x64_bf8_fp8 mlir.dialects.rocdl.wmma_f16_16x16x64_bf8_fp8Adaptor mlir.dialects.rocdl.wmma_f16_16x16x64_fp8_bf8 mlir.dialects.rocdl.wmma_f16_16x16x64_fp8_bf8Adaptor mlir.dialects.rocdl.wmma_f16_16x16x64_fp8_fp8 mlir.dialects.rocdl.wmma_f16_16x16x64_fp8_fp8Adaptor mlir.dialects.rocdl.wmma_f16_16x16x128_bf8_bf8 mlir.dialects.rocdl.wmma_f16_16x16x128_bf8_bf8Adaptor mlir.dialects.rocdl.wmma_f16_16x16x128_bf8_fp8 mlir.dialects.rocdl.wmma_f16_16x16x128_bf8_fp8Adaptor mlir.dialects.rocdl.wmma_f16_16x16x128_fp8_bf8 mlir.dialects.rocdl.wmma_f16_16x16x128_fp8_bf8Adaptor mlir.dialects.rocdl.wmma_f16_16x16x128_fp8_fp8 mlir.dialects.rocdl.wmma_f16_16x16x128_fp8_fp8Adaptor mlir.dialects.rocdl.wmma_f32_16x16x4_f32 mlir.dialects.rocdl.wmma_f32_16x16x4_f32Adaptor mlir.dialects.rocdl.wmma_f32_16x16x16_bf8_bf8 mlir.dialects.rocdl.wmma_f32_16x16x16_bf8_bf8Adaptor mlir.dialects.rocdl.wmma_f32_16x16x16_bf8_fp8 mlir.dialects.rocdl.wmma_f32_16x16x16_bf8_fp8Adaptor mlir.dialects.rocdl.wmma_f32_16x16x16_bf16 mlir.dialects.rocdl.wmma_f32_16x16x16_bf16Adaptor mlir.dialects.rocdl.wmma_f32_16x16x16_f16 mlir.dialects.rocdl.wmma_f32_16x16x16_f16Adaptor mlir.dialects.rocdl.wmma_f32_16x16x16_fp8_bf8 mlir.dialects.rocdl.wmma_f32_16x16x16_fp8_bf8Adaptor mlir.dialects.rocdl.wmma_f32_16x16x16_fp8_fp8 mlir.dialects.rocdl.wmma_f32_16x16x16_fp8_fp8Adaptor mlir.dialects.rocdl.wmma_f32_16x16x32_bf16 mlir.dialects.rocdl.wmma_f32_16x16x32_bf16Adaptor mlir.dialects.rocdl.wmma_f32_16x16x32_f16 mlir.dialects.rocdl.wmma_f32_16x16x32_f16Adaptor mlir.dialects.rocdl.wmma_f32_16x16x64_bf8_bf8 mlir.dialects.rocdl.wmma_f32_16x16x64_bf8_bf8Adaptor mlir.dialects.rocdl.wmma_f32_16x16x64_bf8_fp8 mlir.dialects.rocdl.wmma_f32_16x16x64_bf8_fp8Adaptor mlir.dialects.rocdl.wmma_f32_16x16x64_fp8_bf8 mlir.dialects.rocdl.wmma_f32_16x16x64_fp8_bf8Adaptor mlir.dialects.rocdl.wmma_f32_16x16x64_fp8_fp8 mlir.dialects.rocdl.wmma_f32_16x16x64_fp8_fp8Adaptor mlir.dialects.rocdl.wmma_f32_16x16x128_bf8_bf8 mlir.dialects.rocdl.wmma_f32_16x16x128_bf8_bf8Adaptor mlir.dialects.rocdl.wmma_f32_16x16x128_bf8_fp8 mlir.dialects.rocdl.wmma_f32_16x16x128_bf8_fp8Adaptor mlir.dialects.rocdl.wmma_f32_16x16x128_fp8_bf8 mlir.dialects.rocdl.wmma_f32_16x16x128_fp8_bf8Adaptor mlir.dialects.rocdl.wmma_f32_16x16x128_fp8_fp8 mlir.dialects.rocdl.wmma_f32_16x16x128_fp8_fp8Adaptor mlir.dialects.rocdl.wmma_i32_16x16x16_iu4 mlir.dialects.rocdl.wmma_i32_16x16x16_iu4Adaptor mlir.dialects.rocdl.wmma_i32_16x16x16_iu8 mlir.dialects.rocdl.wmma_i32_16x16x16_iu8Adaptor mlir.dialects.rocdl.wmma_i32_16x16x32_iu4 mlir.dialects.rocdl.wmma_i32_16x16x32_iu4Adaptor mlir.dialects.rocdl.wmma_i32_16x16x64_iu8 mlir.dialects.rocdl.wmma_i32_16x16x64_iu8Adaptor mlir.dialects.rocdl.wmma_scale16_f32_16x16x128_f8f6f4 mlir.dialects.rocdl.wmma_scale16_f32_16x16x128_f8f6f4Adaptor mlir.dialects.rocdl.wmma_scale16_f32_32x16x128_f4 mlir.dialects.rocdl.wmma_scale16_f32_32x16x128_f4Adaptor mlir.dialects.rocdl.wmma_scale_f32_16x16x128_f8f6f4 mlir.dialects.rocdl.wmma_scale_f32_16x16x128_f8f6f4Adaptor mlir.dialects.rocdl.wmma_scale_f32_32x16x128_f4 mlir.dialects.rocdl.wmma_scale_f32_32x16x128_f4Adaptor Functions --------- .. autoapisummary:: mlir.dialects.rocdl.cos mlir.dialects.rocdl.exp mlir.dialects.rocdl.exp2 mlir.dialects.rocdl.log mlir.dialects.rocdl.rcp mlir.dialects.rocdl.rsq mlir.dialects.rocdl.sin mlir.dialects.rocdl.sqrt mlir.dialects.rocdl.tanh mlir.dialects.rocdl.asyncmark mlir.dialects.rocdl.ballot mlir.dialects.rocdl.s_barrier_init mlir.dialects.rocdl.s_barrier_join mlir.dialects.rocdl.s_barrier_leave mlir.dialects.rocdl.barrier mlir.dialects.rocdl.s_barrier_signal_isfirst mlir.dialects.rocdl.s_barrier_signal mlir.dialects.rocdl.s_barrier_signal_var mlir.dialects.rocdl.s_barrier_wait mlir.dialects.rocdl.workgroup_id_x mlir.dialects.rocdl.workgroup_id_y mlir.dialects.rocdl.workgroup_id_z mlir.dialects.rocdl.cluster_id_x mlir.dialects.rocdl.cluster_id_y mlir.dialects.rocdl.cluster_id_z mlir.dialects.rocdl.cluster_load_async_to_lds_b8 mlir.dialects.rocdl.cluster_load_async_to_lds_b32 mlir.dialects.rocdl.cluster_load_async_to_lds_b64 mlir.dialects.rocdl.cluster_load_async_to_lds_b128 mlir.dialects.rocdl.cluster_workgroup_id_x mlir.dialects.rocdl.cluster_workgroup_id_y mlir.dialects.rocdl.cluster_workgroup_id_z mlir.dialects.rocdl.cvt_f32_bf8 mlir.dialects.rocdl.cvt_f32_fp8 mlir.dialects.rocdl.cvt_pk_bf8_f32 mlir.dialects.rocdl.cvt_pk_f32_bf8 mlir.dialects.rocdl.cvt_pk_f32_fp8 mlir.dialects.rocdl.cvt_pk_fp8_f32 mlir.dialects.rocdl.cvt_pkrtz mlir.dialects.rocdl.cvt_scale_pk8_bf16_bf8 mlir.dialects.rocdl.cvt_scale_pk8_bf16_fp4 mlir.dialects.rocdl.cvt_scale_pk8_bf16_fp8 mlir.dialects.rocdl.cvt_scale_pk8_f16_bf8 mlir.dialects.rocdl.cvt_scale_pk8_f16_fp4 mlir.dialects.rocdl.cvt_scale_pk8_f16_fp8 mlir.dialects.rocdl.cvt_scale_pk8_f32_bf8 mlir.dialects.rocdl.cvt_scale_pk8_f32_fp4 mlir.dialects.rocdl.cvt_scale_pk8_f32_fp8 mlir.dialects.rocdl.cvt_scale_pk16_bf16_bf6 mlir.dialects.rocdl.cvt_scale_pk16_bf16_fp6 mlir.dialects.rocdl.cvt_scale_pk16_f16_bf6 mlir.dialects.rocdl.cvt_scale_pk16_f16_fp6 mlir.dialects.rocdl.cvt_scale_pk16_f32_bf6 mlir.dialects.rocdl.cvt_scale_pk16_f32_fp6 mlir.dialects.rocdl.cvt_scalef32_f16_bf8 mlir.dialects.rocdl.cvt_scalef32_f16_fp8 mlir.dialects.rocdl.cvt_scalef32_f32_bf8 mlir.dialects.rocdl.cvt_scalef32_f32_fp8 mlir.dialects.rocdl.cvt_scalef32_pk8_bf8_bf16 mlir.dialects.rocdl.cvt_scalef32_pk8_bf8_f16 mlir.dialects.rocdl.cvt_scalef32_pk8_bf8_f32 mlir.dialects.rocdl.cvt_scalef32_pk8_fp4_bf16 mlir.dialects.rocdl.cvt_scalef32_pk8_fp4_f16 mlir.dialects.rocdl.cvt_scalef32_pk8_fp4_f32 mlir.dialects.rocdl.cvt_scalef32_pk8_fp8_bf16 mlir.dialects.rocdl.cvt_scalef32_pk8_fp8_f16 mlir.dialects.rocdl.cvt_scalef32_pk8_fp8_f32 mlir.dialects.rocdl.cvt_scalef32_pk16_bf6_bf16 mlir.dialects.rocdl.cvt_scalef32_pk16_bf6_f16 mlir.dialects.rocdl.cvt_scalef32_pk16_bf6_f32 mlir.dialects.rocdl.cvt_scalef32_pk16_fp6_bf16 mlir.dialects.rocdl.cvt_scalef32_pk16_fp6_f16 mlir.dialects.rocdl.cvt_scalef32_pk16_fp6_f32 mlir.dialects.rocdl.cvt_scalef32_pk32_bf6_bf16 mlir.dialects.rocdl.cvt_scalef32_pk32_bf6_f16 mlir.dialects.rocdl.cvt_scalef32_pk32_bf16_bf6 mlir.dialects.rocdl.cvt_scalef32_pk32_bf16_fp6 mlir.dialects.rocdl.cvt_scalef32_pk32_f16_bf6 mlir.dialects.rocdl.cvt_scalef32_pk32_f16_fp6 mlir.dialects.rocdl.cvt_scalef32_pk32_f32_bf6 mlir.dialects.rocdl.cvt_scalef32_pk32_f32_fp6 mlir.dialects.rocdl.cvt_scalef32_pk32_fp6_bf16 mlir.dialects.rocdl.cvt_scalef32_pk32_fp6_f16 mlir.dialects.rocdl.cvt_scalef32_pk_bf8_bf16 mlir.dialects.rocdl.cvt_scalef32_pk_bf8_f16 mlir.dialects.rocdl.cvt_scalef32_pk_bf8_f32 mlir.dialects.rocdl.cvt_scalef32_pk_bf16_bf8 mlir.dialects.rocdl.cvt_scalef32_pk_bf16_fp4 mlir.dialects.rocdl.cvt_scalef32_pk_bf16_fp8 mlir.dialects.rocdl.cvt_scalef32_pk_f16_bf8 mlir.dialects.rocdl.cvt_scalef32_pk_f16_fp4 mlir.dialects.rocdl.cvt_scalef32_pk_f16_fp8 mlir.dialects.rocdl.cvt_scalef32_pk_f32_bf8 mlir.dialects.rocdl.cvt_scalef32_pk_f32_fp4 mlir.dialects.rocdl.cvt_scalef32_pk_f32_fp8 mlir.dialects.rocdl.cvt_scalef32_pk_fp4_bf16 mlir.dialects.rocdl.cvt_scalef32_pk_fp4_f16 mlir.dialects.rocdl.cvt_scalef32_pk_fp4_f32 mlir.dialects.rocdl.cvt_scalef32_pk_fp8_bf16 mlir.dialects.rocdl.cvt_scalef32_pk_fp8_f16 mlir.dialects.rocdl.cvt_scalef32_pk_fp8_f32 mlir.dialects.rocdl.cvt_scalef32_sr_bf8_bf16 mlir.dialects.rocdl.cvt_scalef32_sr_bf8_f16 mlir.dialects.rocdl.cvt_scalef32_sr_bf8_f32 mlir.dialects.rocdl.cvt_scalef32_sr_fp8_bf16 mlir.dialects.rocdl.cvt_scalef32_sr_fp8_f16 mlir.dialects.rocdl.cvt_scalef32_sr_fp8_f32 mlir.dialects.rocdl.cvt_scalef32_sr_pk8_bf8_bf16 mlir.dialects.rocdl.cvt_scalef32_sr_pk8_bf8_f16 mlir.dialects.rocdl.cvt_scalef32_sr_pk8_bf8_f32 mlir.dialects.rocdl.cvt_scalef32_sr_pk8_fp4_bf16 mlir.dialects.rocdl.cvt_scalef32_sr_pk8_fp4_f16 mlir.dialects.rocdl.cvt_scalef32_sr_pk8_fp4_f32 mlir.dialects.rocdl.cvt_scalef32_sr_pk8_fp8_bf16 mlir.dialects.rocdl.cvt_scalef32_sr_pk8_fp8_f16 mlir.dialects.rocdl.cvt_scalef32_sr_pk8_fp8_f32 mlir.dialects.rocdl.cvt_scalef32_sr_pk16_bf6_bf16 mlir.dialects.rocdl.cvt_scalef32_sr_pk16_bf6_f16 mlir.dialects.rocdl.cvt_scalef32_sr_pk16_bf6_f32 mlir.dialects.rocdl.cvt_scalef32_sr_pk16_fp6_bf16 mlir.dialects.rocdl.cvt_scalef32_sr_pk16_fp6_f16 mlir.dialects.rocdl.cvt_scalef32_sr_pk16_fp6_f32 mlir.dialects.rocdl.cvt_scalef32_sr_pk32_bf6_bf16 mlir.dialects.rocdl.cvt_scalef32_sr_pk32_bf6_f16 mlir.dialects.rocdl.cvt_scalef32_sr_pk32_bf6_f32 mlir.dialects.rocdl.cvt_scalef32_sr_pk32_fp6_bf16 mlir.dialects.rocdl.cvt_scalef32_sr_pk32_fp6_f16 mlir.dialects.rocdl.cvt_scalef32_sr_pk32_fp6_f32 mlir.dialects.rocdl.cvt_scalef32_sr_pk_fp4_bf16 mlir.dialects.rocdl.cvt_scalef32_sr_pk_fp4_f16 mlir.dialects.rocdl.cvt_scalef32_sr_pk_fp4_f32 mlir.dialects.rocdl.cvt_scalef32_2xpk16_bf6_f32 mlir.dialects.rocdl.cvt_scalef32_2xpk16_fp6_f32 mlir.dialects.rocdl.cvt_sr_bf8_f32 mlir.dialects.rocdl.cvt_sr_fp8_f32 mlir.dialects.rocdl.update_dpp mlir.dialects.rocdl.ds_atomic_async_barrier_arrive_b64 mlir.dialects.rocdl.ds_atomic_barrier_arrive_rtn_b64 mlir.dialects.rocdl.ds_bpermute mlir.dialects.rocdl.ds_load_tr4_b64 mlir.dialects.rocdl.ds_load_tr6_b96 mlir.dialects.rocdl.ds_load_tr8_b64 mlir.dialects.rocdl.ds_load_tr16_b128 mlir.dialects.rocdl.ds_swizzle mlir.dialects.rocdl.fmed3 mlir.dialects.rocdl.flat_prefetch mlir.dialects.rocdl.s_get_barrier_state mlir.dialects.rocdl.s_get_named_barrier_state mlir.dialects.rocdl.global_load_async_lds mlir.dialects.rocdl.global_load_async_to_lds_b8 mlir.dialects.rocdl.global_load_async_to_lds_b32 mlir.dialects.rocdl.global_load_async_to_lds_b64 mlir.dialects.rocdl.global_load_async_to_lds_b128 mlir.dialects.rocdl.global_load_lds mlir.dialects.rocdl.global_load_tr4_b64 mlir.dialects.rocdl.global_load_tr6_b96 mlir.dialects.rocdl.global_load_tr_b64 mlir.dialects.rocdl.global_load_tr_b128 mlir.dialects.rocdl.global_prefetch mlir.dialects.rocdl.global_store_async_from_lds_b8 mlir.dialects.rocdl.global_store_async_from_lds_b32 mlir.dialects.rocdl.global_store_async_from_lds_b64 mlir.dialects.rocdl.global_store_async_from_lds_b128 mlir.dialects.rocdl.iglp_opt mlir.dialects.rocdl.load_async_to_lds mlir.dialects.rocdl.load_to_lds mlir.dialects.rocdl.make_buffer_rsrc mlir.dialects.rocdl.mbcnt_hi mlir.dialects.rocdl.mbcnt_lo mlir.dialects.rocdl.permlane16_swap mlir.dialects.rocdl.permlane16_var mlir.dialects.rocdl.permlane32_swap mlir.dialects.rocdl.permlanex16 mlir.dialects.rocdl.permlanex16_var mlir.dialects.rocdl.ptr_s_buffer_load mlir.dialects.rocdl.raw_buffer_atomic_cmpswap mlir.dialects.rocdl.raw_buffer_atomic_fadd mlir.dialects.rocdl.raw_buffer_atomic_fmax mlir.dialects.rocdl.raw_buffer_atomic_smax mlir.dialects.rocdl.raw_buffer_atomic_umin mlir.dialects.rocdl.raw_buffer_load mlir.dialects.rocdl.raw_buffer_store mlir.dialects.rocdl.raw_ptr_buffer_atomic_cmpswap mlir.dialects.rocdl.raw_ptr_buffer_atomic_fadd mlir.dialects.rocdl.raw_ptr_buffer_atomic_fmax mlir.dialects.rocdl.raw_ptr_buffer_atomic_smax mlir.dialects.rocdl.raw_ptr_buffer_atomic_umin mlir.dialects.rocdl.raw_ptr_buffer_load_async_lds mlir.dialects.rocdl.raw_ptr_buffer_load_lds mlir.dialects.rocdl.raw_ptr_buffer_load mlir.dialects.rocdl.raw_ptr_buffer_store mlir.dialects.rocdl.readfirstlane mlir.dialects.rocdl.readlane mlir.dialects.rocdl.s_barrier mlir.dialects.rocdl.s_nop mlir.dialects.rocdl.s_sleep mlir.dialects.rocdl.s_waitcnt mlir.dialects.rocdl.sched_barrier mlir.dialects.rocdl.sched_group_barrier mlir.dialects.rocdl.s_setprio mlir.dialects.rocdl.tensor_load_to_lds mlir.dialects.rocdl.tensor_store_from_lds mlir.dialects.rocdl.workitem_id_x mlir.dialects.rocdl.workitem_id_y mlir.dialects.rocdl.workitem_id_z mlir.dialects.rocdl.s_wait_asynccnt mlir.dialects.rocdl.wait_asyncmark mlir.dialects.rocdl.s_wait_dscnt mlir.dialects.rocdl.s_wait_expcnt mlir.dialects.rocdl.s_wait_loadcnt mlir.dialects.rocdl.s_wait_storecnt mlir.dialects.rocdl.s_wait_tensorcnt mlir.dialects.rocdl.s_wakeup_barrier mlir.dialects.rocdl.wave_barrier mlir.dialects.rocdl.wave_id mlir.dialects.rocdl.wavefrontsize mlir.dialects.rocdl.dot4_f32_bf8_bf8_ mlir.dialects.rocdl.dot4_f32_bf8_fp8_ mlir.dialects.rocdl.dot4_f32_fp8_bf8_ mlir.dialects.rocdl.dot4_f32_fp8_fp8_ mlir.dialects.rocdl.ds_read_tr4_b64_ mlir.dialects.rocdl.ds_read_tr6_b96_ mlir.dialects.rocdl.ds_read_tr8_b64_ mlir.dialects.rocdl.ds_read_tr16_b64_ mlir.dialects.rocdl.fdot2_ mlir.dialects.rocdl.fdot2_bf16_bf16_ mlir.dialects.rocdl.fdot2_f16_f16_ mlir.dialects.rocdl.fdot2_f32_bf16_ mlir.dialects.rocdl.mfma_f32_4x4x1f32_ mlir.dialects.rocdl.mfma_f32_4x4x2bf16_ mlir.dialects.rocdl.mfma_f32_4x4x4bf16_1k_ mlir.dialects.rocdl.mfma_f32_4x4x4f16_ mlir.dialects.rocdl.mfma_f32_16x16x1f32_ mlir.dialects.rocdl.mfma_f32_16x16x2bf16_ mlir.dialects.rocdl.mfma_f32_16x16x4bf16_1k_ mlir.dialects.rocdl.mfma_f32_16x16x4f16_ mlir.dialects.rocdl.mfma_f32_16x16x4f32_ mlir.dialects.rocdl.mfma_f32_16x16x8_xf32_ mlir.dialects.rocdl.mfma_f32_16x16x8bf16_ mlir.dialects.rocdl.mfma_f32_16x16x16bf16_1k_ mlir.dialects.rocdl.mfma_f32_16x16x16f16_ mlir.dialects.rocdl.mfma_f32_16x16x32_bf8_bf8_ mlir.dialects.rocdl.mfma_f32_16x16x32_bf8_fp8_ mlir.dialects.rocdl.mfma_f32_16x16x32_bf16_ mlir.dialects.rocdl.mfma_f32_16x16x32_f16_ mlir.dialects.rocdl.mfma_f32_16x16x32_fp8_bf8_ mlir.dialects.rocdl.mfma_f32_16x16x32_fp8_fp8_ mlir.dialects.rocdl.mfma_f32_32x32x1f32_ mlir.dialects.rocdl.mfma_f32_32x32x2bf16_ mlir.dialects.rocdl.mfma_f32_32x32x2f32_ mlir.dialects.rocdl.mfma_f32_32x32x4_xf32_ mlir.dialects.rocdl.mfma_f32_32x32x4bf16_ mlir.dialects.rocdl.mfma_f32_32x32x4bf16_1k_ mlir.dialects.rocdl.mfma_f32_32x32x4f16_ mlir.dialects.rocdl.mfma_f32_32x32x8bf16_1k_ mlir.dialects.rocdl.mfma_f32_32x32x8f16_ mlir.dialects.rocdl.mfma_f32_32x32x16_bf8_bf8_ mlir.dialects.rocdl.mfma_f32_32x32x16_bf8_fp8_ mlir.dialects.rocdl.mfma_f32_32x32x16_bf16_ mlir.dialects.rocdl.mfma_f32_32x32x16_f16_ mlir.dialects.rocdl.mfma_f32_32x32x16_fp8_bf8_ mlir.dialects.rocdl.mfma_f32_32x32x16_fp8_fp8_ mlir.dialects.rocdl.mfma_f64_4x4x4f64_ mlir.dialects.rocdl.mfma_f64_16x16x4f64_ mlir.dialects.rocdl.mfma_i32_4x4x4i8_ mlir.dialects.rocdl.mfma_i32_16x16x4i8_ mlir.dialects.rocdl.mfma_i32_16x16x16i8_ mlir.dialects.rocdl.mfma_i32_16x16x32_i8_ mlir.dialects.rocdl.mfma_i32_16x16x64_i8_ mlir.dialects.rocdl.mfma_i32_32x32x4i8_ mlir.dialects.rocdl.mfma_i32_32x32x8i8_ mlir.dialects.rocdl.mfma_i32_32x32x16_i8_ mlir.dialects.rocdl.mfma_i32_32x32x32_i8_ mlir.dialects.rocdl.mfma_scale_f32_16x16x128_f8f6f4_ mlir.dialects.rocdl.mfma_scale_f32_32x32x64_f8f6f4_ mlir.dialects.rocdl.sdot2_ mlir.dialects.rocdl.sdot4_ mlir.dialects.rocdl.sdot8_ mlir.dialects.rocdl.smfmac_f32_16x16x32_bf16_ mlir.dialects.rocdl.smfmac_f32_16x16x32_f16_ mlir.dialects.rocdl.smfmac_f32_16x16x64_bf8_bf8_ mlir.dialects.rocdl.smfmac_f32_16x16x64_bf8_fp8_ mlir.dialects.rocdl.smfmac_f32_16x16x64_bf16_ mlir.dialects.rocdl.smfmac_f32_16x16x64_f16_ mlir.dialects.rocdl.smfmac_f32_16x16x64_fp8_bf8_ mlir.dialects.rocdl.smfmac_f32_16x16x64_fp8_fp8_ mlir.dialects.rocdl.smfmac_f32_16x16x128_bf8_bf8_ mlir.dialects.rocdl.smfmac_f32_16x16x128_bf8_fp8_ mlir.dialects.rocdl.smfmac_f32_16x16x128_fp8_bf8_ mlir.dialects.rocdl.smfmac_f32_16x16x128_fp8_fp8_ mlir.dialects.rocdl.smfmac_f32_32x32x16_bf16_ mlir.dialects.rocdl.smfmac_f32_32x32x16_f16_ mlir.dialects.rocdl.smfmac_f32_32x32x32_bf8_bf8_ mlir.dialects.rocdl.smfmac_f32_32x32x32_bf8_fp8_ mlir.dialects.rocdl.smfmac_f32_32x32x32_bf16_ mlir.dialects.rocdl.smfmac_f32_32x32x32_f16_ mlir.dialects.rocdl.smfmac_f32_32x32x32_fp8_bf8_ mlir.dialects.rocdl.smfmac_f32_32x32x32_fp8_fp8_ mlir.dialects.rocdl.smfmac_f32_32x32x64_bf8_bf8_ mlir.dialects.rocdl.smfmac_f32_32x32x64_bf8_fp8_ mlir.dialects.rocdl.smfmac_f32_32x32x64_fp8_bf8_ mlir.dialects.rocdl.smfmac_f32_32x32x64_fp8_fp8_ mlir.dialects.rocdl.smfmac_i32_16x16x64_i8_ mlir.dialects.rocdl.smfmac_i32_16x16x128_i8_ mlir.dialects.rocdl.smfmac_i32_32x32x32_i8_ mlir.dialects.rocdl.smfmac_i32_32x32x64_i8_ mlir.dialects.rocdl.sudot4_ mlir.dialects.rocdl.sudot8_ mlir.dialects.rocdl.swmmac_bf16_16x16x32_bf16_ mlir.dialects.rocdl.swmmac_bf16_16x16x64_bf16_ mlir.dialects.rocdl.swmmac_bf16f32_16x16x64_bf16_ mlir.dialects.rocdl.swmmac_f16_16x16x32_f16_ mlir.dialects.rocdl.swmmac_f16_16x16x64_f16_ mlir.dialects.rocdl.swmmac_f16_16x16x128_bf8_bf8_ mlir.dialects.rocdl.swmmac_f16_16x16x128_bf8_fp8_ mlir.dialects.rocdl.swmmac_f16_16x16x128_fp8_bf8_ mlir.dialects.rocdl.swmmac_f16_16x16x128_fp8_fp8_ mlir.dialects.rocdl.swmmac_f32_16x16x32_bf8_bf8_ mlir.dialects.rocdl.swmmac_f32_16x16x32_bf8_fp8_ mlir.dialects.rocdl.swmmac_f32_16x16x32_bf16_ mlir.dialects.rocdl.swmmac_f32_16x16x32_f16_ mlir.dialects.rocdl.swmmac_f32_16x16x32_fp8_bf8_ mlir.dialects.rocdl.swmmac_f32_16x16x32_fp8_fp8_ mlir.dialects.rocdl.swmmac_f32_16x16x64_bf16_ mlir.dialects.rocdl.swmmac_f32_16x16x64_f16_ mlir.dialects.rocdl.swmmac_f32_16x16x128_bf8_bf8_ mlir.dialects.rocdl.swmmac_f32_16x16x128_bf8_fp8_ mlir.dialects.rocdl.swmmac_f32_16x16x128_fp8_bf8_ mlir.dialects.rocdl.swmmac_f32_16x16x128_fp8_fp8_ mlir.dialects.rocdl.swmmac_i32_16x16x32_iu4_ mlir.dialects.rocdl.swmmac_i32_16x16x32_iu8_ mlir.dialects.rocdl.swmmac_i32_16x16x64_iu4_ mlir.dialects.rocdl.swmmac_i32_16x16x128_iu8_ mlir.dialects.rocdl.udot2_ mlir.dialects.rocdl.udot4_ mlir.dialects.rocdl.udot8_ mlir.dialects.rocdl.wmma_bf16_16x16x16_bf16_ mlir.dialects.rocdl.wmma_bf16_16x16x32_bf16_ mlir.dialects.rocdl.wmma_bf16f32_16x16x32_bf16_ mlir.dialects.rocdl.wmma_f16_16x16x16_f16_ mlir.dialects.rocdl.wmma_f16_16x16x32_f16_ mlir.dialects.rocdl.wmma_f16_16x16x64_bf8_bf8_ mlir.dialects.rocdl.wmma_f16_16x16x64_bf8_fp8_ mlir.dialects.rocdl.wmma_f16_16x16x64_fp8_bf8_ mlir.dialects.rocdl.wmma_f16_16x16x64_fp8_fp8_ mlir.dialects.rocdl.wmma_f16_16x16x128_bf8_bf8_ mlir.dialects.rocdl.wmma_f16_16x16x128_bf8_fp8_ mlir.dialects.rocdl.wmma_f16_16x16x128_fp8_bf8_ mlir.dialects.rocdl.wmma_f16_16x16x128_fp8_fp8_ mlir.dialects.rocdl.wmma_f32_16x16x4_f32_ mlir.dialects.rocdl.wmma_f32_16x16x16_bf8_bf8_ mlir.dialects.rocdl.wmma_f32_16x16x16_bf8_fp8_ mlir.dialects.rocdl.wmma_f32_16x16x16_bf16_ mlir.dialects.rocdl.wmma_f32_16x16x16_f16_ mlir.dialects.rocdl.wmma_f32_16x16x16_fp8_bf8_ mlir.dialects.rocdl.wmma_f32_16x16x16_fp8_fp8_ mlir.dialects.rocdl.wmma_f32_16x16x32_bf16_ mlir.dialects.rocdl.wmma_f32_16x16x32_f16_ mlir.dialects.rocdl.wmma_f32_16x16x64_bf8_bf8_ mlir.dialects.rocdl.wmma_f32_16x16x64_bf8_fp8_ mlir.dialects.rocdl.wmma_f32_16x16x64_fp8_bf8_ mlir.dialects.rocdl.wmma_f32_16x16x64_fp8_fp8_ mlir.dialects.rocdl.wmma_f32_16x16x128_bf8_bf8_ mlir.dialects.rocdl.wmma_f32_16x16x128_bf8_fp8_ mlir.dialects.rocdl.wmma_f32_16x16x128_fp8_bf8_ mlir.dialects.rocdl.wmma_f32_16x16x128_fp8_fp8_ mlir.dialects.rocdl.wmma_i32_16x16x16_iu4_ mlir.dialects.rocdl.wmma_i32_16x16x16_iu8_ mlir.dialects.rocdl.wmma_i32_16x16x32_iu4_ mlir.dialects.rocdl.wmma_i32_16x16x64_iu8_ mlir.dialects.rocdl.wmma_scale16_f32_16x16x128_f8f6f4_ mlir.dialects.rocdl.wmma_scale16_f32_32x16x128_f4_ mlir.dialects.rocdl.wmma_scale_f32_16x16x128_f8f6f4_ mlir.dialects.rocdl.wmma_scale_f32_32x16x128_f4_ Module Contents --------------- .. py:class:: ROCDLCos(res: _ods_ir, arg: _ods_ir, *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Note: In the general case, prefer the conventional ``arith``, ``math``, or ``llvm`` ops over this. Use this ROCDL-specific operation only when you fully understand its implication and when it is strictly necessary. This op is usually chosen when a small loss in precision is acceptable in exchange for higher execution speed. Example: .. code:: mlir %0 = rocdl.cos %a f32 -> f32 .. py:attribute:: OPERATION_NAME :value: 'rocdl.cos' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: arg() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: ROCDLCosAdaptor(operands: list[Value], attributes: OpAttributeMap) ROCDLCosAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cos' .. py:method:: arg() -> _ods_ir .. py:function:: cos(res: _ods_ir, arg: _ods_ir, *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: ROCDLExp(res: _ods_ir, arg: _ods_ir, *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Note: In the general case, prefer the conventional ``arith``, ``math``, or ``llvm`` ops over this. Use this ROCDL-specific operation only when you fully understand its implication and when it is strictly necessary. This op is usually chosen when a small loss in precision is acceptable in exchange for higher execution speed. Example: .. code:: mlir %0 = rocdl.exp %a f32 -> f32 .. py:attribute:: OPERATION_NAME :value: 'rocdl.exp' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: arg() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: ROCDLExpAdaptor(operands: list[Value], attributes: OpAttributeMap) ROCDLExpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.exp' .. py:method:: arg() -> _ods_ir .. py:function:: exp(res: _ods_ir, arg: _ods_ir, *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: ROCDLExp2(res: _ods_ir, arg: _ods_ir, *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Note: In the general case, prefer the conventional ``arith``, ``math``, or ``llvm`` ops over this. Use this ROCDL-specific operation only when you fully understand its implication and when it is strictly necessary. This op is usually chosen when a small loss in precision is acceptable in exchange for higher execution speed. Example: .. code:: mlir %0 = rocdl.exp2 %a f32 -> f32 .. py:attribute:: OPERATION_NAME :value: 'rocdl.exp2' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: arg() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: ROCDLExp2Adaptor(operands: list[Value], attributes: OpAttributeMap) ROCDLExp2Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.exp2' .. py:method:: arg() -> _ods_ir .. py:function:: exp2(res: _ods_ir, arg: _ods_ir, *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: ROCDLLog(res: _ods_ir, arg: _ods_ir, *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Note: In the general case, prefer the conventional ``arith``, ``math``, or ``llvm`` ops over this. Use this ROCDL-specific operation only when you fully understand its implication and when it is strictly necessary. This op is usually chosen when a small loss in precision is acceptable in exchange for higher execution speed. Example: .. code:: mlir %0 = rocdl.log %a f32 -> f32 .. py:attribute:: OPERATION_NAME :value: 'rocdl.log' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: arg() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: ROCDLLogAdaptor(operands: list[Value], attributes: OpAttributeMap) ROCDLLogAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.log' .. py:method:: arg() -> _ods_ir .. py:function:: log(res: _ods_ir, arg: _ods_ir, *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: ROCDLRcp(res: _ods_ir, arg: _ods_ir, *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Note: In the general case, prefer the conventional ``arith``, ``math``, or ``llvm`` ops over this. Use this ROCDL-specific operation only when you fully understand its implication and when it is strictly necessary. This op is usually chosen when a small loss in precision is acceptable in exchange for higher execution speed. Example: .. code:: mlir %0 = rocdl.rcp %a f32 -> f32 .. py:attribute:: OPERATION_NAME :value: 'rocdl.rcp' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: arg() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: ROCDLRcpAdaptor(operands: list[Value], attributes: OpAttributeMap) ROCDLRcpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.rcp' .. py:method:: arg() -> _ods_ir .. py:function:: rcp(res: _ods_ir, arg: _ods_ir, *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: ROCDLRsq(res: _ods_ir, arg: _ods_ir, *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Note: In the general case, prefer the conventional ``arith``, ``math``, or ``llvm`` ops over this. Use this ROCDL-specific operation only when you fully understand its implication and when it is strictly necessary. This op is usually chosen when a small loss in precision is acceptable in exchange for higher execution speed. Example: .. code:: mlir %0 = rocdl.rsq %a f32 -> f32 .. py:attribute:: OPERATION_NAME :value: 'rocdl.rsq' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: arg() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: ROCDLRsqAdaptor(operands: list[Value], attributes: OpAttributeMap) ROCDLRsqAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.rsq' .. py:method:: arg() -> _ods_ir .. py:function:: rsq(res: _ods_ir, arg: _ods_ir, *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: ROCDLSin(res: _ods_ir, arg: _ods_ir, *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Note: In the general case, prefer the conventional ``arith``, ``math``, or ``llvm`` ops over this. Use this ROCDL-specific operation only when you fully understand its implication and when it is strictly necessary. This op is usually chosen when a small loss in precision is acceptable in exchange for higher execution speed. Example: .. code:: mlir %0 = rocdl.sin %a f32 -> f32 .. py:attribute:: OPERATION_NAME :value: 'rocdl.sin' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: arg() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: ROCDLSinAdaptor(operands: list[Value], attributes: OpAttributeMap) ROCDLSinAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.sin' .. py:method:: arg() -> _ods_ir .. py:function:: sin(res: _ods_ir, arg: _ods_ir, *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: ROCDLSqrt(res: _ods_ir, arg: _ods_ir, *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Note: In the general case, prefer the conventional ``arith``, ``math``, or ``llvm`` ops over this. Use this ROCDL-specific operation only when you fully understand its implication and when it is strictly necessary. This op is usually chosen when a small loss in precision is acceptable in exchange for higher execution speed. Example: .. code:: mlir %0 = rocdl.sqrt %a f32 -> f32 .. py:attribute:: OPERATION_NAME :value: 'rocdl.sqrt' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: arg() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: ROCDLSqrtAdaptor(operands: list[Value], attributes: OpAttributeMap) ROCDLSqrtAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.sqrt' .. py:method:: arg() -> _ods_ir .. py:function:: sqrt(res: _ods_ir, arg: _ods_ir, *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: ROCDLTanh(res: _ods_ir, arg: _ods_ir, *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Note: In the general case, prefer the conventional ``arith``, ``math``, or ``llvm`` ops over this. Use this ROCDL-specific operation only when you fully understand its implication and when it is strictly necessary. This op is usually chosen when a small loss in precision is acceptable in exchange for higher execution speed. Example: .. code:: mlir %0 = rocdl.tanh %a f32 -> f32 .. py:attribute:: OPERATION_NAME :value: 'rocdl.tanh' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: arg() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: ROCDLTanhAdaptor(operands: list[Value], attributes: OpAttributeMap) ROCDLTanhAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.tanh' .. py:method:: arg() -> _ods_ir .. py:function:: tanh(res: _ods_ir, arg: _ods_ir, *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: AsyncmarkOp(*, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` This operation, in conjunction with ``rocdl.wait.asyncmark``, forms the compiler-provided framework for tracking explicitly asynchronous memory operations, such as copies to LDS that use async intrinsics and gfx1250's tensor loads. Details of its behavior can be found in `the LLVM documentation on async tracking `_. See ``rocdl.wait.asyncmark``'s documentation for a usage example. Example: .. code:: mlir // Mark the end of an async operation group. rocdl.asyncmark Available on gfx9 and later. .. py:attribute:: OPERATION_NAME :value: 'rocdl.asyncmark' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:class:: AsyncmarkOpAdaptor(operands: list[Value], attributes: OpAttributeMap) AsyncmarkOpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.asyncmark' .. py:function:: asyncmark(*, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> AsyncmarkOp .. py:class:: BallotOp(res: _ods_ir, pred: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Ballot provides a bit mask containing the 1-bit predicate value from each lane. The nth bit of the result contains the 1 bit contributed by the nth warp lane. Example: .. code:: mlir // Ballot across thread group. %0 = rocdl.ballot %pred : i64 .. py:attribute:: OPERATION_NAME :value: 'rocdl.ballot' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: pred() -> _ods_ir[_ods_ir] .. py:method:: res() -> _ods_ir .. py:class:: BallotOpAdaptor(operands: list[Value], attributes: OpAttributeMap) BallotOpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.ballot' .. py:method:: pred() -> _ods_ir[_ods_ir] .. py:function:: ballot(res: _ods_ir, pred: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: BarrierInitOp(ptr: _ods_ir, memberCnt: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Available on gfx1250+. Example: .. code:: mlir // Initialize a named barrier with member count. rocdl.s.barrier.init %ptr member_cnt = 1 : !llvm.ptr<3> .. py:attribute:: OPERATION_NAME :value: 'rocdl.s.barrier.init' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: ptr() -> _ods_ir .. py:method:: memberCnt() -> _ods_ir .. py:class:: BarrierInitOpAdaptor(operands: list[Value], attributes: OpAttributeMap) BarrierInitOpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.s.barrier.init' .. py:method:: ptr() -> _ods_ir .. py:method:: memberCnt() -> _ods_ir .. py:function:: s_barrier_init(ptr: _ods_ir, member_cnt: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> BarrierInitOp .. py:class:: BarrierJoinOp(ptr: _ods_ir, *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Available on gfx1250+. Example: .. code:: mlir // Join a named barrier. rocdl.s.barrier.join %ptr : !llvm.ptr<3> .. py:attribute:: OPERATION_NAME :value: 'rocdl.s.barrier.join' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: ptr() -> _ods_ir .. py:class:: BarrierJoinOpAdaptor(operands: list[Value], attributes: OpAttributeMap) BarrierJoinOpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.s.barrier.join' .. py:method:: ptr() -> _ods_ir .. py:function:: s_barrier_join(ptr: _ods_ir, *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> BarrierJoinOp .. py:class:: BarrierLeaveOp(id: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Available on gfx1250+. Example: .. code:: mlir // Leave a named barrier by id. rocdl.s.barrier.leave id = 1 .. py:attribute:: OPERATION_NAME :value: 'rocdl.s.barrier.leave' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: id() -> _ods_ir .. py:class:: BarrierLeaveOpAdaptor(operands: list[Value], attributes: OpAttributeMap) BarrierLeaveOpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.s.barrier.leave' .. py:method:: id() -> _ods_ir .. py:function:: s_barrier_leave(id: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> BarrierLeaveOp .. py:class:: BarrierOp(*, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` An operation with the same expansion as HIP's __synchthreads(); **DEPRECATION NOTICE**: Use ``gpu.barrier``, which will expand to these operations, instead. Example: .. code:: mlir // Workgroup barrier with acquire/release fences. rocdl.barrier .. py:attribute:: OPERATION_NAME :value: 'rocdl.barrier' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:class:: BarrierOpAdaptor(operands: list[Value], attributes: OpAttributeMap) BarrierOpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.barrier' .. py:function:: barrier(*, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> BarrierOp .. py:class:: BarrierSignalIsfirstOp(res: _ods_ir, id: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Available on gfx1200+. Example: .. code:: mlir // Signal barrier and check if this wave is first to arrive. %0 = rocdl.s.barrier.signal.isfirst id = 1 -> i1 .. py:attribute:: OPERATION_NAME :value: 'rocdl.s.barrier.signal.isfirst' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: id() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: BarrierSignalIsfirstOpAdaptor(operands: list[Value], attributes: OpAttributeMap) BarrierSignalIsfirstOpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.s.barrier.signal.isfirst' .. py:method:: id() -> _ods_ir .. py:function:: s_barrier_signal_isfirst(res: _ods_ir, id: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: BarrierSignalOp(id: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Signal a barrier by id. Available on gfx1250+. Example: .. code:: mlir // Signal barrier with id -1 (all barriers). rocdl.s.barrier.signal id = -1 .. py:attribute:: OPERATION_NAME :value: 'rocdl.s.barrier.signal' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: id() -> _ods_ir .. py:class:: BarrierSignalOpAdaptor(operands: list[Value], attributes: OpAttributeMap) BarrierSignalOpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.s.barrier.signal' .. py:method:: id() -> _ods_ir .. py:function:: s_barrier_signal(id: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> BarrierSignalOp .. py:class:: BarrierSignalVarOp(ptr: _ods_ir, memberCnt: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Available on gfx1250+. If ``memberCnt`` is 0, the member count is retained from a previous initialization. Example: .. code:: mlir // Signal a named barrier with variable ID. rocdl.s.barrier.signal.var %ptr member_cnt = 1 : !llvm.ptr<3> .. py:attribute:: OPERATION_NAME :value: 'rocdl.s.barrier.signal.var' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: ptr() -> _ods_ir .. py:method:: memberCnt() -> _ods_ir .. py:class:: BarrierSignalVarOpAdaptor(operands: list[Value], attributes: OpAttributeMap) BarrierSignalVarOpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.s.barrier.signal.var' .. py:method:: ptr() -> _ods_ir .. py:method:: memberCnt() -> _ods_ir .. py:function:: s_barrier_signal_var(ptr: _ods_ir, member_cnt: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> BarrierSignalVarOp .. py:class:: BarrierWaitOp(id: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Wait on a barrier by id. Available on gfx1200+. Example: .. code:: mlir // Wait on barrier with id -1 (all barriers). rocdl.s.barrier.wait id = -1 .. py:attribute:: OPERATION_NAME :value: 'rocdl.s.barrier.wait' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: id() -> _ods_ir .. py:class:: BarrierWaitOpAdaptor(operands: list[Value], attributes: OpAttributeMap) BarrierWaitOpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.s.barrier.wait' .. py:method:: id() -> _ods_ir .. py:function:: s_barrier_wait(id: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> BarrierWaitOp .. py:class:: BlockIdXOp(res: _ods_ir, *, range: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Read a hardware register for thread/workgroup/cluster identification. An optional ``range`` attribute can constrain the returned value. Example: .. code:: mlir // Read the workitem id in the x dimension. %0 = rocdl.workitem.id.x : i32 // Read with a known range constraint. %1 = rocdl.workitem.id.x range : i32 .. py:attribute:: OPERATION_NAME :value: 'rocdl.workgroup.id.x' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: range() -> Optional[_ods_ir] .. py:method:: res() -> _ods_ir .. py:class:: BlockIdXOpAdaptor(operands: list[Value], attributes: OpAttributeMap) BlockIdXOpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.workgroup.id.x' .. py:method:: range() -> Optional[_ods_ir] .. py:function:: workgroup_id_x(res: _ods_ir, *, range: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: BlockIdYOp(res: _ods_ir, *, range: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Read a hardware register for thread/workgroup/cluster identification. An optional ``range`` attribute can constrain the returned value. Example: .. code:: mlir // Read the workitem id in the x dimension. %0 = rocdl.workitem.id.x : i32 // Read with a known range constraint. %1 = rocdl.workitem.id.x range : i32 .. py:attribute:: OPERATION_NAME :value: 'rocdl.workgroup.id.y' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: range() -> Optional[_ods_ir] .. py:method:: res() -> _ods_ir .. py:class:: BlockIdYOpAdaptor(operands: list[Value], attributes: OpAttributeMap) BlockIdYOpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.workgroup.id.y' .. py:method:: range() -> Optional[_ods_ir] .. py:function:: workgroup_id_y(res: _ods_ir, *, range: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: BlockIdZOp(res: _ods_ir, *, range: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Read a hardware register for thread/workgroup/cluster identification. An optional ``range`` attribute can constrain the returned value. Example: .. code:: mlir // Read the workitem id in the x dimension. %0 = rocdl.workitem.id.x : i32 // Read with a known range constraint. %1 = rocdl.workitem.id.x range : i32 .. py:attribute:: OPERATION_NAME :value: 'rocdl.workgroup.id.z' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: range() -> Optional[_ods_ir] .. py:method:: res() -> _ods_ir .. py:class:: BlockIdZOpAdaptor(operands: list[Value], attributes: OpAttributeMap) BlockIdZOpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.workgroup.id.z' .. py:method:: range() -> Optional[_ods_ir] .. py:function:: workgroup_id_z(res: _ods_ir, *, range: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: ClusterIdXOp(res: _ods_ir, *, range: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Read a hardware register for thread/workgroup/cluster identification. An optional ``range`` attribute can constrain the returned value. Example: .. code:: mlir // Read the workitem id in the x dimension. %0 = rocdl.workitem.id.x : i32 // Read with a known range constraint. %1 = rocdl.workitem.id.x range : i32 .. py:attribute:: OPERATION_NAME :value: 'rocdl.cluster.id.x' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: range() -> Optional[_ods_ir] .. py:method:: res() -> _ods_ir .. py:class:: ClusterIdXOpAdaptor(operands: list[Value], attributes: OpAttributeMap) ClusterIdXOpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cluster.id.x' .. py:method:: range() -> Optional[_ods_ir] .. py:function:: cluster_id_x(res: _ods_ir, *, range: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: ClusterIdYOp(res: _ods_ir, *, range: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Read a hardware register for thread/workgroup/cluster identification. An optional ``range`` attribute can constrain the returned value. Example: .. code:: mlir // Read the workitem id in the x dimension. %0 = rocdl.workitem.id.x : i32 // Read with a known range constraint. %1 = rocdl.workitem.id.x range : i32 .. py:attribute:: OPERATION_NAME :value: 'rocdl.cluster.id.y' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: range() -> Optional[_ods_ir] .. py:method:: res() -> _ods_ir .. py:class:: ClusterIdYOpAdaptor(operands: list[Value], attributes: OpAttributeMap) ClusterIdYOpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cluster.id.y' .. py:method:: range() -> Optional[_ods_ir] .. py:function:: cluster_id_y(res: _ods_ir, *, range: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: ClusterIdZOp(res: _ods_ir, *, range: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Read a hardware register for thread/workgroup/cluster identification. An optional ``range`` attribute can constrain the returned value. Example: .. code:: mlir // Read the workitem id in the x dimension. %0 = rocdl.workitem.id.x : i32 // Read with a known range constraint. %1 = rocdl.workitem.id.x range : i32 .. py:attribute:: OPERATION_NAME :value: 'rocdl.cluster.id.z' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: range() -> Optional[_ods_ir] .. py:method:: res() -> _ods_ir .. py:class:: ClusterIdZOpAdaptor(operands: list[Value], attributes: OpAttributeMap) ClusterIdZOpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cluster.id.z' .. py:method:: range() -> Optional[_ods_ir] .. py:function:: cluster_id_z(res: _ods_ir, *, range: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: ClusterLoadAsyncToLDSB8Op(globalPtr: _ods_ir, ldsPtr: _ods_ir, offset: Union[int, _ods_ir], mask: _ods_ir[_ods_ir], *, cpol: Optional[Union[Any, _ods_ir]] = None, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Broadcasts memory load of 8 bits of data for a cluster of workgroups. Available on gfx1250+. Example: .. code:: mlir // Cluster broadcast 8-bit load to LDS. rocdl.cluster.load.async.to.lds.b8 %src, %dst, 0, 0, %mask : !llvm.ptr<1>, !llvm.ptr<3> .. py:attribute:: OPERATION_NAME :value: 'rocdl.cluster.load.async.to.lds.b8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: globalPtr() -> _ods_ir .. py:method:: ldsPtr() -> _ods_ir .. py:method:: mask() -> _ods_ir[_ods_ir] .. py:method:: offset() -> _ods_ir .. py:method:: cpol() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:class:: ClusterLoadAsyncToLDSB8OpAdaptor(operands: list[Value], attributes: OpAttributeMap) ClusterLoadAsyncToLDSB8OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cluster.load.async.to.lds.b8' .. py:method:: globalPtr() -> _ods_ir .. py:method:: ldsPtr() -> _ods_ir .. py:method:: mask() -> _ods_ir[_ods_ir] .. py:method:: offset() -> _ods_ir .. py:method:: cpol() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:function:: cluster_load_async_to_lds_b8(global_ptr: _ods_ir, lds_ptr: _ods_ir, offset: Union[int, _ods_ir], mask: _ods_ir[_ods_ir], *, cpol: Optional[Union[Any, _ods_ir]] = None, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> ClusterLoadAsyncToLDSB8Op .. py:class:: ClusterLoadAsyncToLDSB32Op(globalPtr: _ods_ir, ldsPtr: _ods_ir, offset: Union[int, _ods_ir], mask: _ods_ir[_ods_ir], *, cpol: Optional[Union[Any, _ods_ir]] = None, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Broadcasts memory load of 32 bits of data for a cluster of workgroups. Available on gfx1250+. Example: .. code:: mlir // Cluster broadcast 32-bit load to LDS. rocdl.cluster.load.async.to.lds.b32 %src, %dst, 0, 0, %mask : !llvm.ptr<1>, !llvm.ptr<3> .. py:attribute:: OPERATION_NAME :value: 'rocdl.cluster.load.async.to.lds.b32' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: globalPtr() -> _ods_ir .. py:method:: ldsPtr() -> _ods_ir .. py:method:: mask() -> _ods_ir[_ods_ir] .. py:method:: offset() -> _ods_ir .. py:method:: cpol() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:class:: ClusterLoadAsyncToLDSB32OpAdaptor(operands: list[Value], attributes: OpAttributeMap) ClusterLoadAsyncToLDSB32OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cluster.load.async.to.lds.b32' .. py:method:: globalPtr() -> _ods_ir .. py:method:: ldsPtr() -> _ods_ir .. py:method:: mask() -> _ods_ir[_ods_ir] .. py:method:: offset() -> _ods_ir .. py:method:: cpol() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:function:: cluster_load_async_to_lds_b32(global_ptr: _ods_ir, lds_ptr: _ods_ir, offset: Union[int, _ods_ir], mask: _ods_ir[_ods_ir], *, cpol: Optional[Union[Any, _ods_ir]] = None, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> ClusterLoadAsyncToLDSB32Op .. py:class:: ClusterLoadAsyncToLDSB64Op(globalPtr: _ods_ir, ldsPtr: _ods_ir, offset: Union[int, _ods_ir], mask: _ods_ir[_ods_ir], *, cpol: Optional[Union[Any, _ods_ir]] = None, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Broadcasts memory load of 64 bits of data for a cluster of workgroups. Available on gfx1250+. Example: .. code:: mlir // Cluster broadcast 64-bit load to LDS. rocdl.cluster.load.async.to.lds.b64 %src, %dst, 0, 0, %mask : !llvm.ptr<1>, !llvm.ptr<3> .. py:attribute:: OPERATION_NAME :value: 'rocdl.cluster.load.async.to.lds.b64' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: globalPtr() -> _ods_ir .. py:method:: ldsPtr() -> _ods_ir .. py:method:: mask() -> _ods_ir[_ods_ir] .. py:method:: offset() -> _ods_ir .. py:method:: cpol() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:class:: ClusterLoadAsyncToLDSB64OpAdaptor(operands: list[Value], attributes: OpAttributeMap) ClusterLoadAsyncToLDSB64OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cluster.load.async.to.lds.b64' .. py:method:: globalPtr() -> _ods_ir .. py:method:: ldsPtr() -> _ods_ir .. py:method:: mask() -> _ods_ir[_ods_ir] .. py:method:: offset() -> _ods_ir .. py:method:: cpol() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:function:: cluster_load_async_to_lds_b64(global_ptr: _ods_ir, lds_ptr: _ods_ir, offset: Union[int, _ods_ir], mask: _ods_ir[_ods_ir], *, cpol: Optional[Union[Any, _ods_ir]] = None, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> ClusterLoadAsyncToLDSB64Op .. py:class:: ClusterLoadAsyncToLDSB128Op(globalPtr: _ods_ir, ldsPtr: _ods_ir, offset: Union[int, _ods_ir], mask: _ods_ir[_ods_ir], *, cpol: Optional[Union[Any, _ods_ir]] = None, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Broadcasts memory load of 128 bits of data for a cluster of workgroups. Available on gfx1250+. Example: .. code:: mlir // Cluster broadcast 128-bit load to LDS. rocdl.cluster.load.async.to.lds.b128 %src, %dst, 0, 0, %mask : !llvm.ptr<1>, !llvm.ptr<3> .. py:attribute:: OPERATION_NAME :value: 'rocdl.cluster.load.async.to.lds.b128' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: globalPtr() -> _ods_ir .. py:method:: ldsPtr() -> _ods_ir .. py:method:: mask() -> _ods_ir[_ods_ir] .. py:method:: offset() -> _ods_ir .. py:method:: cpol() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:class:: ClusterLoadAsyncToLDSB128OpAdaptor(operands: list[Value], attributes: OpAttributeMap) ClusterLoadAsyncToLDSB128OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cluster.load.async.to.lds.b128' .. py:method:: globalPtr() -> _ods_ir .. py:method:: ldsPtr() -> _ods_ir .. py:method:: mask() -> _ods_ir[_ods_ir] .. py:method:: offset() -> _ods_ir .. py:method:: cpol() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:function:: cluster_load_async_to_lds_b128(global_ptr: _ods_ir, lds_ptr: _ods_ir, offset: Union[int, _ods_ir], mask: _ods_ir[_ods_ir], *, cpol: Optional[Union[Any, _ods_ir]] = None, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> ClusterLoadAsyncToLDSB128Op .. py:class:: ClusterWorkgroupIdXOp(res: _ods_ir, *, range: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Read a hardware register for thread/workgroup/cluster identification. An optional ``range`` attribute can constrain the returned value. Example: .. code:: mlir // Read the workitem id in the x dimension. %0 = rocdl.workitem.id.x : i32 // Read with a known range constraint. %1 = rocdl.workitem.id.x range : i32 .. py:attribute:: OPERATION_NAME :value: 'rocdl.cluster.workgroup.id.x' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: range() -> Optional[_ods_ir] .. py:method:: res() -> _ods_ir .. py:class:: ClusterWorkgroupIdXOpAdaptor(operands: list[Value], attributes: OpAttributeMap) ClusterWorkgroupIdXOpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cluster.workgroup.id.x' .. py:method:: range() -> Optional[_ods_ir] .. py:function:: cluster_workgroup_id_x(res: _ods_ir, *, range: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: ClusterWorkgroupIdYOp(res: _ods_ir, *, range: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Read a hardware register for thread/workgroup/cluster identification. An optional ``range`` attribute can constrain the returned value. Example: .. code:: mlir // Read the workitem id in the x dimension. %0 = rocdl.workitem.id.x : i32 // Read with a known range constraint. %1 = rocdl.workitem.id.x range : i32 .. py:attribute:: OPERATION_NAME :value: 'rocdl.cluster.workgroup.id.y' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: range() -> Optional[_ods_ir] .. py:method:: res() -> _ods_ir .. py:class:: ClusterWorkgroupIdYOpAdaptor(operands: list[Value], attributes: OpAttributeMap) ClusterWorkgroupIdYOpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cluster.workgroup.id.y' .. py:method:: range() -> Optional[_ods_ir] .. py:function:: cluster_workgroup_id_y(res: _ods_ir, *, range: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: ClusterWorkgroupIdZOp(res: _ods_ir, *, range: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Read a hardware register for thread/workgroup/cluster identification. An optional ``range`` attribute can constrain the returned value. Example: .. code:: mlir // Read the workitem id in the x dimension. %0 = rocdl.workitem.id.x : i32 // Read with a known range constraint. %1 = rocdl.workitem.id.x range : i32 .. py:attribute:: OPERATION_NAME :value: 'rocdl.cluster.workgroup.id.z' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: range() -> Optional[_ods_ir] .. py:method:: res() -> _ods_ir .. py:class:: ClusterWorkgroupIdZOpAdaptor(operands: list[Value], attributes: OpAttributeMap) ClusterWorkgroupIdZOpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cluster.workgroup.id.z' .. py:method:: range() -> Optional[_ods_ir] .. py:function:: cluster_workgroup_id_z(res: _ods_ir, *, range: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: CvtF32Bf8Op(res: _ods_ir, srcA: _ods_ir[_ods_ir], byteSel: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert 8-bit bf8 value from the ``byteSel``th bit of ``srcA`` to fp32. Example: .. code:: mlir // Convert bf8 byte 0 to f32. %0 = rocdl.cvt.f32.bf8 %src[0] : f32 .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.f32.bf8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: srcA() -> _ods_ir[_ods_ir] .. py:method:: byteSel() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: CvtF32Bf8OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtF32Bf8OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.f32.bf8' .. py:method:: srcA() -> _ods_ir[_ods_ir] .. py:method:: byteSel() -> _ods_ir .. py:function:: cvt_f32_bf8(res: _ods_ir, src_a: _ods_ir[_ods_ir], byte_sel: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: CvtF32Fp8Op(res: _ods_ir, srcA: _ods_ir[_ods_ir], byteSel: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert 8-bit fp8 value from the ``byteSel``th bit of ``srcA`` to fp32. Example: .. code:: mlir // Convert fp8 byte 0 to f32. %0 = rocdl.cvt.f32.fp8 %src[0] : f32 .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.f32.fp8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: srcA() -> _ods_ir[_ods_ir] .. py:method:: byteSel() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: CvtF32Fp8OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtF32Fp8OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.f32.fp8' .. py:method:: srcA() -> _ods_ir[_ods_ir] .. py:method:: byteSel() -> _ods_ir .. py:function:: cvt_f32_fp8(res: _ods_ir, src_a: _ods_ir[_ods_ir], byte_sel: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: CvtPkBf8F32Op(res: _ods_ir, srcA: _ods_ir[_ods_ir], srcB: _ods_ir[_ods_ir], old: _ods_ir[_ods_ir], wordSel: Union[bool, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert ``srcA`` and ``srcB`` to bf8 and store into the low/high word of ``old``, preserving the other word. Example: .. code:: mlir // Pack two f32 values into bf8 in the low word of old. %0 = rocdl.cvt.pk.bf8.f32 %a, %b -> %old[false] : i32 .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.pk.bf8.f32' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: srcA() -> _ods_ir[_ods_ir] .. py:method:: srcB() -> _ods_ir[_ods_ir] .. py:method:: old() -> _ods_ir[_ods_ir] .. py:method:: wordSel() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: CvtPkBf8F32OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtPkBf8F32OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.pk.bf8.f32' .. py:method:: srcA() -> _ods_ir[_ods_ir] .. py:method:: srcB() -> _ods_ir[_ods_ir] .. py:method:: old() -> _ods_ir[_ods_ir] .. py:method:: wordSel() -> _ods_ir .. py:function:: cvt_pk_bf8_f32(res: _ods_ir, src_a: _ods_ir[_ods_ir], src_b: _ods_ir[_ods_ir], old: _ods_ir[_ods_ir], word_sel: Union[bool, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: CvtPkF32Bf8Op(res: _ods_ir, src: _ods_ir[_ods_ir], wordSel: Union[bool, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert ``src`` based on $wordSel to packed fp32. Example: .. code:: mlir // Unpack bf8 word to packed f32. %0 = rocdl.cvt.pk.f32.bf8 %src[false] : vector<2xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.pk.f32.bf8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: wordSel() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: CvtPkF32Bf8OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtPkF32Bf8OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.pk.f32.bf8' .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: wordSel() -> _ods_ir .. py:function:: cvt_pk_f32_bf8(res: _ods_ir, src: _ods_ir[_ods_ir], word_sel: Union[bool, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: CvtPkF32Fp8Op(res: _ods_ir, src: _ods_ir[_ods_ir], wordSel: Union[bool, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert ``src`` based on $wordSel to packed fp32. Example: .. code:: mlir // Unpack fp8 word to packed f32. %0 = rocdl.cvt.pk.f32.fp8 %src[false] : vector<2xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.pk.f32.fp8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: wordSel() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: CvtPkF32Fp8OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtPkF32Fp8OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.pk.f32.fp8' .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: wordSel() -> _ods_ir .. py:function:: cvt_pk_f32_fp8(res: _ods_ir, src: _ods_ir[_ods_ir], word_sel: Union[bool, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: CvtPkFp8F32Op(res: _ods_ir, srcA: _ods_ir[_ods_ir], srcB: _ods_ir[_ods_ir], old: _ods_ir[_ods_ir], wordSel: Union[bool, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert ``srcA`` and ``srcB`` to fp8 and store into the low/high word of ``old``, preserving the other word. Example: .. code:: mlir // Pack two f32 values into fp8 in the low word of old. %0 = rocdl.cvt.pk.fp8.f32 %a, %b -> %old[false] : i32 .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.pk.fp8.f32' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: srcA() -> _ods_ir[_ods_ir] .. py:method:: srcB() -> _ods_ir[_ods_ir] .. py:method:: old() -> _ods_ir[_ods_ir] .. py:method:: wordSel() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: CvtPkFp8F32OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtPkFp8F32OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.pk.fp8.f32' .. py:method:: srcA() -> _ods_ir[_ods_ir] .. py:method:: srcB() -> _ods_ir[_ods_ir] .. py:method:: old() -> _ods_ir[_ods_ir] .. py:method:: wordSel() -> _ods_ir .. py:function:: cvt_pk_fp8_f32(res: _ods_ir, src_a: _ods_ir[_ods_ir], src_b: _ods_ir[_ods_ir], old: _ods_ir[_ods_ir], word_sel: Union[bool, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: CvtPkRtz(res: _ods_ir, srcA: _ods_ir[_ods_ir], srcB: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert two f32 values into a packed vector<2xf16>. Example: .. code:: mlir // Pack two f32 values into a vector<2xf16> with round-to-zero. %0 = rocdl.cvt.pkrtz %a, %b : vector<2xf16> .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.pkrtz' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: srcA() -> _ods_ir[_ods_ir] .. py:method:: srcB() -> _ods_ir[_ods_ir] .. py:method:: res() -> _ods_ir .. py:class:: CvtPkRtzAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtPkRtzAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.pkrtz' .. py:method:: srcA() -> _ods_ir[_ods_ir] .. py:method:: srcB() -> _ods_ir[_ods_ir] .. py:function:: cvt_pkrtz(res: _ods_ir, src_a: _ods_ir[_ods_ir], src_b: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: CvtPkScalePk8Bf16Bf8Op(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], scaleSel: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Available on gfx1250+. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scale.pk8.bf16.bf8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: scaleSel() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtPkScalePk8Bf16Bf8OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtPkScalePk8Bf16Bf8OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scale.pk8.bf16.bf8' .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: scaleSel() -> _ods_ir .. py:function:: cvt_scale_pk8_bf16_bf8(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], scale_sel: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtPkScalePk8Bf16Fp4Op(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], scaleSel: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Available on gfx1250+. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scale.pk8.bf16.fp4' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: scaleSel() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtPkScalePk8Bf16Fp4OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtPkScalePk8Bf16Fp4OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scale.pk8.bf16.fp4' .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: scaleSel() -> _ods_ir .. py:function:: cvt_scale_pk8_bf16_fp4(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], scale_sel: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtPkScalePk8Bf16Fp8Op(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], scaleSel: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Available on gfx1250+. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scale.pk8.bf16.fp8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: scaleSel() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtPkScalePk8Bf16Fp8OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtPkScalePk8Bf16Fp8OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scale.pk8.bf16.fp8' .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: scaleSel() -> _ods_ir .. py:function:: cvt_scale_pk8_bf16_fp8(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], scale_sel: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtPkScalePk8F16Bf8Op(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], scaleSel: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Available on gfx1250+. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scale.pk8.f16.bf8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: scaleSel() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtPkScalePk8F16Bf8OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtPkScalePk8F16Bf8OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scale.pk8.f16.bf8' .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: scaleSel() -> _ods_ir .. py:function:: cvt_scale_pk8_f16_bf8(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], scale_sel: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtPkScalePk8F16Fp4Op(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], scaleSel: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Available on gfx1250+. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scale.pk8.f16.fp4' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: scaleSel() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtPkScalePk8F16Fp4OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtPkScalePk8F16Fp4OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scale.pk8.f16.fp4' .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: scaleSel() -> _ods_ir .. py:function:: cvt_scale_pk8_f16_fp4(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], scale_sel: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtPkScalePk8F16Fp8Op(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], scaleSel: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Available on gfx1250+. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scale.pk8.f16.fp8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: scaleSel() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtPkScalePk8F16Fp8OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtPkScalePk8F16Fp8OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scale.pk8.f16.fp8' .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: scaleSel() -> _ods_ir .. py:function:: cvt_scale_pk8_f16_fp8(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], scale_sel: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtPkScalePk8F32Bf8Op(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], scaleSel: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Available on gfx1250+. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scale.pk8.f32.bf8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: scaleSel() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtPkScalePk8F32Bf8OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtPkScalePk8F32Bf8OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scale.pk8.f32.bf8' .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: scaleSel() -> _ods_ir .. py:function:: cvt_scale_pk8_f32_bf8(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], scale_sel: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtPkScalePk8F32Fp4Op(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], scaleSel: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Available on gfx1250+. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scale.pk8.f32.fp4' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: scaleSel() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtPkScalePk8F32Fp4OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtPkScalePk8F32Fp4OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scale.pk8.f32.fp4' .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: scaleSel() -> _ods_ir .. py:function:: cvt_scale_pk8_f32_fp4(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], scale_sel: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtPkScalePk8F32Fp8Op(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], scaleSel: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Available on gfx1250+. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scale.pk8.f32.fp8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: scaleSel() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtPkScalePk8F32Fp8OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtPkScalePk8F32Fp8OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scale.pk8.f32.fp8' .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: scaleSel() -> _ods_ir .. py:function:: cvt_scale_pk8_f32_fp8(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], scale_sel: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtPkScalePk16Bf16Bf6Op(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], scaleSel: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Available on gfx1250+. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scale.pk16.bf16.bf6' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: scaleSel() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtPkScalePk16Bf16Bf6OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtPkScalePk16Bf16Bf6OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scale.pk16.bf16.bf6' .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: scaleSel() -> _ods_ir .. py:function:: cvt_scale_pk16_bf16_bf6(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], scale_sel: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtPkScalePk16Bf16Fp6Op(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], scaleSel: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Available on gfx1250+. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scale.pk16.bf16.fp6' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: scaleSel() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtPkScalePk16Bf16Fp6OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtPkScalePk16Bf16Fp6OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scale.pk16.bf16.fp6' .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: scaleSel() -> _ods_ir .. py:function:: cvt_scale_pk16_bf16_fp6(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], scale_sel: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtPkScalePk16F16Bf6Op(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], scaleSel: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Available on gfx1250+. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scale.pk16.f16.bf6' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: scaleSel() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtPkScalePk16F16Bf6OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtPkScalePk16F16Bf6OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scale.pk16.f16.bf6' .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: scaleSel() -> _ods_ir .. py:function:: cvt_scale_pk16_f16_bf6(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], scale_sel: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtPkScalePk16F16Fp6Op(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], scaleSel: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Available on gfx1250+. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scale.pk16.f16.fp6' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: scaleSel() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtPkScalePk16F16Fp6OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtPkScalePk16F16Fp6OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scale.pk16.f16.fp6' .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: scaleSel() -> _ods_ir .. py:function:: cvt_scale_pk16_f16_fp6(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], scale_sel: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtPkScalePk16F32Bf6Op(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], scaleSel: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Available on gfx1250+. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scale.pk16.f32.bf6' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: scaleSel() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtPkScalePk16F32Bf6OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtPkScalePk16F32Bf6OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scale.pk16.f32.bf6' .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: scaleSel() -> _ods_ir .. py:function:: cvt_scale_pk16_f32_bf6(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], scale_sel: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtPkScalePk16F32Fp6Op(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], scaleSel: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Available on gfx1250+. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scale.pk16.f32.fp6' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: scaleSel() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtPkScalePk16F32Fp6OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtPkScalePk16F32Fp6OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scale.pk16.f32.fp6' .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: scaleSel() -> _ods_ir .. py:function:: cvt_scale_pk16_f32_fp6(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], scale_sel: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32F16Bf8Op(res: _ods_ir, oldVdst: _ods_ir[_ods_ir], src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], srcSelIndex: Union[int, _ods_ir], dstLoHiSel: Union[bool, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert a bf8 byte from ``src``, selected by ``srcSelIndex``, to f16 while multiplying it by the expontent of ``scale``, and place it into the ``dstLoHiSel``th bit of ``oldVdst`` preserving the other element of that vector in the return value. The bytes are stored as an ``i32`` and not a ``<4 x i8>``. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.f16.bf8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: oldVdst() -> _ods_ir[_ods_ir] .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: srcSelIndex() -> _ods_ir .. py:method:: dstLoHiSel() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32F16Bf8OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtScaleF32F16Bf8OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.f16.bf8' .. py:method:: oldVdst() -> _ods_ir[_ods_ir] .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: srcSelIndex() -> _ods_ir .. py:method:: dstLoHiSel() -> _ods_ir .. py:function:: cvt_scalef32_f16_bf8(res: _ods_ir, old_vdst: _ods_ir[_ods_ir], src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], src_sel_index: Union[int, _ods_ir], dst_lo_hi_sel: Union[bool, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32F16Fp8Op(res: _ods_ir, oldVdst: _ods_ir[_ods_ir], src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], srcSelIndex: Union[int, _ods_ir], dstLoHiSel: Union[bool, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert a fp8 byte from ``src``, selected by ``srcSelIndex``, to f16 while multiplying it by the expontent of ``scale``, and place it into the ``dstLoHiSel``th bit of ``oldVdst`` preserving the other element of that vector in the return value. The bytes are stored as an ``i32`` and not a ``<4 x i8>``. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.f16.fp8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: oldVdst() -> _ods_ir[_ods_ir] .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: srcSelIndex() -> _ods_ir .. py:method:: dstLoHiSel() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32F16Fp8OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtScaleF32F16Fp8OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.f16.fp8' .. py:method:: oldVdst() -> _ods_ir[_ods_ir] .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: srcSelIndex() -> _ods_ir .. py:method:: dstLoHiSel() -> _ods_ir .. py:function:: cvt_scalef32_f16_fp8(res: _ods_ir, old_vdst: _ods_ir[_ods_ir], src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], src_sel_index: Union[int, _ods_ir], dst_lo_hi_sel: Union[bool, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32F32Bf8Op(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], srcSelIndex: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert a bf8 byte from ``src``, selected by ``srcSelIndex``, to f32, multiplying it by the exponent of ``scale``. The bytes are stored in an ``i32``, not a ``<4 x i8>``. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.f32.bf8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: srcSelIndex() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32F32Bf8OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtScaleF32F32Bf8OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.f32.bf8' .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: srcSelIndex() -> _ods_ir .. py:function:: cvt_scalef32_f32_bf8(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], src_sel_index: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32F32Fp8Op(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], srcSelIndex: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert a fp8 byte from ``src``, selected by ``srcSelIndex``, to f32, multiplying it by the exponent of ``scale``. The bytes are stored in an ``i32``, not a ``<4 x i8>``. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.f32.fp8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: srcSelIndex() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32F32Fp8OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtScaleF32F32Fp8OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.f32.fp8' .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: srcSelIndex() -> _ods_ir .. py:function:: cvt_scalef32_f32_fp8(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], src_sel_index: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32Pk8Bf8Bf16Op(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert 8 packed bf16 values to packed bf8, multiplying by the exponent part of ``scale`` before doing so. This op is for gfx1250+ arch. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk8.bf8.bf16' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32Pk8Bf8Bf16OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtScaleF32Pk8Bf8Bf16OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk8.bf8.bf16' .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:function:: cvt_scalef32_pk8_bf8_bf16(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32Pk8Bf8F16Op(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert 8 packed f16 values to packed bf8, multiplying by the exponent part of ``scale`` before doing so. This op is for gfx1250+ arch. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk8.bf8.f16' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32Pk8Bf8F16OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtScaleF32Pk8Bf8F16OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk8.bf8.f16' .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:function:: cvt_scalef32_pk8_bf8_f16(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32Pk8Bf8F32Op(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert 8 packed f32 values to packed bf8, multiplying by the exponent part of ``scale`` before doing so. This op is for gfx1250+ arch. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk8.bf8.f32' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32Pk8Bf8F32OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtScaleF32Pk8Bf8F32OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk8.bf8.f32' .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:function:: cvt_scalef32_pk8_bf8_f32(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32Pk8Fp4Bf16Op(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert 8 packed bf16 values to packed fp4, multiplying by the exponent part of ``scale`` before doing so. This op is for gfx1250+ arch. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk8.fp4.bf16' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32Pk8Fp4Bf16OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtScaleF32Pk8Fp4Bf16OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk8.fp4.bf16' .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:function:: cvt_scalef32_pk8_fp4_bf16(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32Pk8Fp4F16Op(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert 8 packed f16 values to packed fp4, multiplying by the exponent part of ``scale`` before doing so. This op is for gfx1250+ arch. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk8.fp4.f16' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32Pk8Fp4F16OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtScaleF32Pk8Fp4F16OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk8.fp4.f16' .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:function:: cvt_scalef32_pk8_fp4_f16(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32Pk8Fp4F32Op(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert 8 packed f32 values to packed fp4, multiplying by the exponent part of ``scale`` before doing so. This op is for gfx1250+ arch. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk8.fp4.f32' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32Pk8Fp4F32OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtScaleF32Pk8Fp4F32OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk8.fp4.f32' .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:function:: cvt_scalef32_pk8_fp4_f32(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32Pk8Fp8Bf16Op(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert 8 packed bf16 values to packed fp8, multiplying by the exponent part of ``scale`` before doing so. This op is for gfx1250+ arch. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk8.fp8.bf16' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32Pk8Fp8Bf16OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtScaleF32Pk8Fp8Bf16OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk8.fp8.bf16' .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:function:: cvt_scalef32_pk8_fp8_bf16(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32Pk8Fp8F16Op(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert 8 packed f16 values to packed fp8, multiplying by the exponent part of ``scale`` before doing so. This op is for gfx1250+ arch. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk8.fp8.f16' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32Pk8Fp8F16OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtScaleF32Pk8Fp8F16OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk8.fp8.f16' .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:function:: cvt_scalef32_pk8_fp8_f16(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32Pk8Fp8F32Op(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert 8 packed f32 values to packed fp8, multiplying by the exponent part of ``scale`` before doing so. This op is for gfx1250+ arch. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk8.fp8.f32' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32Pk8Fp8F32OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtScaleF32Pk8Fp8F32OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk8.fp8.f32' .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:function:: cvt_scalef32_pk8_fp8_f32(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32Pk16Bf6Bf16Op(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert 8 packed bf16 values to packed bf6, multiplying by the exponent part of ``scale`` before doing so. This op is for gfx1250+ arch. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk16.bf6.bf16' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32Pk16Bf6Bf16OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtScaleF32Pk16Bf6Bf16OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk16.bf6.bf16' .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:function:: cvt_scalef32_pk16_bf6_bf16(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32Pk16Bf6F16Op(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert 8 packed f16 values to packed bf6, multiplying by the exponent part of ``scale`` before doing so. This op is for gfx1250+ arch. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk16.bf6.f16' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32Pk16Bf6F16OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtScaleF32Pk16Bf6F16OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk16.bf6.f16' .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:function:: cvt_scalef32_pk16_bf6_f16(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32Pk16Bf6F32Op(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert 8 packed f32 values to packed bf6, multiplying by the exponent part of ``scale`` before doing so. This op is for gfx1250+ arch. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk16.bf6.f32' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32Pk16Bf6F32OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtScaleF32Pk16Bf6F32OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk16.bf6.f32' .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:function:: cvt_scalef32_pk16_bf6_f32(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32Pk16Fp6Bf16Op(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert 8 packed bf16 values to packed fp6, multiplying by the exponent part of ``scale`` before doing so. This op is for gfx1250+ arch. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk16.fp6.bf16' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32Pk16Fp6Bf16OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtScaleF32Pk16Fp6Bf16OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk16.fp6.bf16' .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:function:: cvt_scalef32_pk16_fp6_bf16(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32Pk16Fp6F16Op(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert 8 packed f16 values to packed fp6, multiplying by the exponent part of ``scale`` before doing so. This op is for gfx1250+ arch. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk16.fp6.f16' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32Pk16Fp6F16OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtScaleF32Pk16Fp6F16OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk16.fp6.f16' .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:function:: cvt_scalef32_pk16_fp6_f16(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32Pk16Fp6F32Op(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert 8 packed f32 values to packed fp6, multiplying by the exponent part of ``scale`` before doing so. This op is for gfx1250+ arch. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk16.fp6.f32' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32Pk16Fp6F32OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtScaleF32Pk16Fp6F32OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk16.fp6.f32' .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:function:: cvt_scalef32_pk16_fp6_f32(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32Pk32Bf6Bf16Op(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert 32 packed bf16 values to packed bf6, dividing by the exponent part of ``scale`` before doing so. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk32.bf6.bf16' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32Pk32Bf6Bf16OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtScaleF32Pk32Bf6Bf16OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk32.bf6.bf16' .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:function:: cvt_scalef32_pk32_bf6_bf16(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32Pk32Bf6F16Op(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert 32 packed f16 values to packed bf6, dividing by the exponent part of ``scale`` before doing so. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk32.bf6.f16' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32Pk32Bf6F16OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtScaleF32Pk32Bf6F16OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk32.bf6.f16' .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:function:: cvt_scalef32_pk32_bf6_f16(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32Pk32Bf16Bf6Op(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert 32 packed bf6 values to packed bf16, multiplying by the exponent part of ``scale`` before doing so. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk32.bf16.bf6' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32Pk32Bf16Bf6OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtScaleF32Pk32Bf16Bf6OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk32.bf16.bf6' .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:function:: cvt_scalef32_pk32_bf16_bf6(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32Pk32Bf16Fp6Op(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert 32 packed fp6 values to packed bf16, multiplying by the exponent part of ``scale`` before doing so. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk32.bf16.fp6' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32Pk32Bf16Fp6OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtScaleF32Pk32Bf16Fp6OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk32.bf16.fp6' .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:function:: cvt_scalef32_pk32_bf16_fp6(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32Pk32F16Bf6Op(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert 32 packed bf6 values to packed f16, multiplying by the exponent part of ``scale`` before doing so. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk32.f16.bf6' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32Pk32F16Bf6OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtScaleF32Pk32F16Bf6OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk32.f16.bf6' .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:function:: cvt_scalef32_pk32_f16_bf6(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32Pk32F16Fp6Op(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert 32 packed fp6 values to packed f16, multiplying by the exponent part of ``scale`` before doing so. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk32.f16.fp6' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32Pk32F16Fp6OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtScaleF32Pk32F16Fp6OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk32.f16.fp6' .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:function:: cvt_scalef32_pk32_f16_fp6(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32Pk32F32Bf6Op(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert 32 packed bf6 values to packed f32, multiplying by the exponent part of ``scale`` before doing so. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk32.f32.bf6' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32Pk32F32Bf6OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtScaleF32Pk32F32Bf6OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk32.f32.bf6' .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:function:: cvt_scalef32_pk32_f32_bf6(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32Pk32F32Fp6Op(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert 32 packed fp6 values to packed f32, multiplying by the exponent part of ``scale`` before doing so. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk32.f32.fp6' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32Pk32F32Fp6OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtScaleF32Pk32F32Fp6OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk32.f32.fp6' .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:function:: cvt_scalef32_pk32_f32_fp6(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32Pk32Fp6Bf16Op(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert 32 packed bf16 values to packed fp6, dividing by the exponent part of ``scale`` before doing so. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk32.fp6.bf16' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32Pk32Fp6Bf16OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtScaleF32Pk32Fp6Bf16OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk32.fp6.bf16' .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:function:: cvt_scalef32_pk32_fp6_bf16(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32Pk32Fp6F16Op(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert 32 packed f16 values to packed fp6, dividing by the exponent part of ``scale`` before doing so. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk32.fp6.f16' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32Pk32Fp6F16OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtScaleF32Pk32Fp6F16OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk32.fp6.f16' .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:function:: cvt_scalef32_pk32_fp6_f16(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32PkBf8Bf16Op(res: _ods_ir, oldVdst: _ods_ir[_ods_ir], src0: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], dstLoHiSel: Union[bool, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert two bf16 values in ``src0`` to two bf8 bytes, dividing by the exponent in ``scale``. The bytes are packed into a 16-bit value which is inserted into ``oldVdst`` at the ``dstLoHiSel`` position, with the entire updated vector being returned. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk.bf8.bf16' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: oldVdst() -> _ods_ir[_ods_ir] .. py:method:: src0() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: dstLoHiSel() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32PkBf8Bf16OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtScaleF32PkBf8Bf16OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk.bf8.bf16' .. py:method:: oldVdst() -> _ods_ir[_ods_ir] .. py:method:: src0() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: dstLoHiSel() -> _ods_ir .. py:function:: cvt_scalef32_pk_bf8_bf16(res: _ods_ir, old_vdst: _ods_ir[_ods_ir], src0: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], dst_lo_hi_sel: Union[bool, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32PkBf8F16Op(res: _ods_ir, oldVdst: _ods_ir[_ods_ir], src0: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], dstLoHiSel: Union[bool, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert two f16 values in ``src0`` to two bf8 bytes, dividing by the exponent in ``scale``. The bytes are packed into a 16-bit value which is inserted into ``oldVdst`` at the ``dstLoHiSel`` position, with the entire updated vector being returned. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk.bf8.f16' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: oldVdst() -> _ods_ir[_ods_ir] .. py:method:: src0() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: dstLoHiSel() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32PkBf8F16OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtScaleF32PkBf8F16OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk.bf8.f16' .. py:method:: oldVdst() -> _ods_ir[_ods_ir] .. py:method:: src0() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: dstLoHiSel() -> _ods_ir .. py:function:: cvt_scalef32_pk_bf8_f16(res: _ods_ir, old_vdst: _ods_ir[_ods_ir], src0: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], dst_lo_hi_sel: Union[bool, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32PkBf8F32Op(res: _ods_ir, oldVdst: _ods_ir[_ods_ir], src0: _ods_ir[_ods_ir], src1: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], dstLoHiSel: Union[bool, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert two f32 values in ``src0`` and ``src1`` to two bf8 bytes, dividing by the exponent in ``scale``. The bytes are packed into a 16-bit value which is inserted into ``oldVdst`` at the ``dstLoHiSel`` position, with the entire updated vector being returned. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk.bf8.f32' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: oldVdst() -> _ods_ir[_ods_ir] .. py:method:: src0() -> _ods_ir[_ods_ir] .. py:method:: src1() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: dstLoHiSel() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32PkBf8F32OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtScaleF32PkBf8F32OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk.bf8.f32' .. py:method:: oldVdst() -> _ods_ir[_ods_ir] .. py:method:: src0() -> _ods_ir[_ods_ir] .. py:method:: src1() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: dstLoHiSel() -> _ods_ir .. py:function:: cvt_scalef32_pk_bf8_f32(res: _ods_ir, old_vdst: _ods_ir[_ods_ir], src0: _ods_ir[_ods_ir], src1: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], dst_lo_hi_sel: Union[bool, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32PkBf16Bf8Op(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], srcLoHiSel: Union[bool, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert two packed bf8 values in ``src0`` to two bf16 values, multiplying by the exponent in ``scale``. The two values to be converted are selected from the low or high half of ``src`` (a packed vector represented as an ``i32``) on the basis of ``srcLoHiSel``. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk.bf16.bf8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: srcLoHiSel() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32PkBf16Bf8OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtScaleF32PkBf16Bf8OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk.bf16.bf8' .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: srcLoHiSel() -> _ods_ir .. py:function:: cvt_scalef32_pk_bf16_bf8(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], src_lo_hi_sel: Union[bool, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32PkBf16Fp4Op(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], srcSelIndex: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert two packed fp4 (f4E2M1) values stored as one byte of a 32-bit integer to packed bf16, multiplying by the exponent part of ``scale`` before doing so. The byte to convert is chosen by ``srcSelIndex``. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk.bf16.fp4' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: srcSelIndex() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32PkBf16Fp4OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtScaleF32PkBf16Fp4OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk.bf16.fp4' .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: srcSelIndex() -> _ods_ir .. py:function:: cvt_scalef32_pk_bf16_fp4(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], src_sel_index: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32PkBf16Fp8Op(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], srcLoHiSel: Union[bool, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert two packed fp8 values in ``src0`` to two bf16 values, multiplying by the exponent in ``scale``. The two values to be converted are selected from the low or high half of ``src`` (a packed vector represented as an ``i32``) on the basis of ``srcLoHiSel``. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk.bf16.fp8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: srcLoHiSel() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32PkBf16Fp8OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtScaleF32PkBf16Fp8OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk.bf16.fp8' .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: srcLoHiSel() -> _ods_ir .. py:function:: cvt_scalef32_pk_bf16_fp8(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], src_lo_hi_sel: Union[bool, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32PkF16Bf8Op(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], srcLoHiSel: Union[bool, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert two packed bf8 values in ``src0`` to two f16 values, multiplying by the exponent in ``scale``. The two values to be converted are selected from the low or high half of ``src`` (a packed vector represented as an ``i32``) on the basis of ``srcLoHiSel``. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk.f16.bf8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: srcLoHiSel() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32PkF16Bf8OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtScaleF32PkF16Bf8OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk.f16.bf8' .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: srcLoHiSel() -> _ods_ir .. py:function:: cvt_scalef32_pk_f16_bf8(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], src_lo_hi_sel: Union[bool, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32PkF16Fp4Op(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], srcSelIndex: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert two packed fp4 (f4E2M1) values stored as one byte of a 32-bit integer to packed f16, multiplying by the exponent part of ``scale`` before doing so. The byte to convert is chosen by ``srcSelIndex``. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk.f16.fp4' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: srcSelIndex() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32PkF16Fp4OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtScaleF32PkF16Fp4OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk.f16.fp4' .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: srcSelIndex() -> _ods_ir .. py:function:: cvt_scalef32_pk_f16_fp4(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], src_sel_index: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32PkF16Fp8Op(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], srcLoHiSel: Union[bool, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert two packed fp8 values in ``src0`` to two f16 values, multiplying by the exponent in ``scale``. The two values to be converted are selected from the low or high half of ``src`` (a packed vector represented as an ``i32``) on the basis of ``srcLoHiSel``. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk.f16.fp8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: srcLoHiSel() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32PkF16Fp8OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtScaleF32PkF16Fp8OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk.f16.fp8' .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: srcLoHiSel() -> _ods_ir .. py:function:: cvt_scalef32_pk_f16_fp8(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], src_lo_hi_sel: Union[bool, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32PkF32Bf8Op(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], srcLoHiSel: Union[bool, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert two packed bf8 values in ``src0`` to two f32 values, multiplying by the exponent in ``scale``. The two values to be converted are selected from the low or high half of ``src`` (a packed vector represented as an ``i32``) on the basis of ``srcLoHiSel``. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk.f32.bf8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: srcLoHiSel() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32PkF32Bf8OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtScaleF32PkF32Bf8OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk.f32.bf8' .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: srcLoHiSel() -> _ods_ir .. py:function:: cvt_scalef32_pk_f32_bf8(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], src_lo_hi_sel: Union[bool, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32PkF32Fp4Op(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], srcSelIndex: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert two packed fp4 (f4E2M1) values stored as one byte of a 32-bit integer to packed f32, multiplying by the exponent part of ``scale`` before doing so. The byte to convert is chosen by ``srcSelIndex``. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk.f32.fp4' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: srcSelIndex() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32PkF32Fp4OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtScaleF32PkF32Fp4OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk.f32.fp4' .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: srcSelIndex() -> _ods_ir .. py:function:: cvt_scalef32_pk_f32_fp4(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], src_sel_index: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32PkF32Fp8Op(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], srcLoHiSel: Union[bool, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert two packed fp8 values in ``src0`` to two f32 values, multiplying by the exponent in ``scale``. The two values to be converted are selected from the low or high half of ``src`` (a packed vector represented as an ``i32``) on the basis of ``srcLoHiSel``. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk.f32.fp8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: srcLoHiSel() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32PkF32Fp8OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtScaleF32PkF32Fp8OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk.f32.fp8' .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: srcLoHiSel() -> _ods_ir .. py:function:: cvt_scalef32_pk_f32_fp8(res: _ods_ir, src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], src_lo_hi_sel: Union[bool, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32PkFp4Bf16Op(res: _ods_ir, oldVdst: _ods_ir[_ods_ir], src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], dstSelIndex: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert two packed bf16 values to packed fp4, dividing by the exponent part of ``scale`` before doing so. The two scaled values are packed into a byte. That byte is used to update the ``dstSelIndex``th byte of ``oldVdst``, which is returned in its entirity. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk.fp4.bf16' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: oldVdst() -> _ods_ir[_ods_ir] .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: dstSelIndex() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32PkFp4Bf16OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtScaleF32PkFp4Bf16OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk.fp4.bf16' .. py:method:: oldVdst() -> _ods_ir[_ods_ir] .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: dstSelIndex() -> _ods_ir .. py:function:: cvt_scalef32_pk_fp4_bf16(res: _ods_ir, old_vdst: _ods_ir[_ods_ir], src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], dst_sel_index: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32PkFp4F16Op(res: _ods_ir, oldVdst: _ods_ir[_ods_ir], src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], dstSelIndex: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert two packed f16 values to packed fp4, dividing by the exponent part of ``scale`` before doing so. The two scaled values are packed into a byte. That byte is used to update the ``dstSelIndex``th byte of ``oldVdst``, which is returned in its entirity. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk.fp4.f16' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: oldVdst() -> _ods_ir[_ods_ir] .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: dstSelIndex() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32PkFp4F16OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtScaleF32PkFp4F16OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk.fp4.f16' .. py:method:: oldVdst() -> _ods_ir[_ods_ir] .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: dstSelIndex() -> _ods_ir .. py:function:: cvt_scalef32_pk_fp4_f16(res: _ods_ir, old_vdst: _ods_ir[_ods_ir], src: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], dst_sel_index: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32PkFp4F32Op(res: _ods_ir, oldVdst: _ods_ir[_ods_ir], src0: _ods_ir[_ods_ir], src1: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], dstSelIndex: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert two single-precision float values, passed in ``src0`` and ``src1`` into two fp4 values, dividing them by the expontent part of ``scale`` before doing so. The two scaled values are packed into a byte. That byte is used to update the ``dstSelIndex``th byte of ``oldVdst``, which is returned in its entirity. Example: .. code:: mlir // Scaled convert two f32 values to packed fp4 in byte 0 of old. %0 = rocdl.cvt.scalef32.pk.fp4.f32 %a, %b, %scale -> %old[0] : i32 .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk.fp4.f32' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: oldVdst() -> _ods_ir[_ods_ir] .. py:method:: src0() -> _ods_ir[_ods_ir] .. py:method:: src1() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: dstSelIndex() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32PkFp4F32OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtScaleF32PkFp4F32OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk.fp4.f32' .. py:method:: oldVdst() -> _ods_ir[_ods_ir] .. py:method:: src0() -> _ods_ir[_ods_ir] .. py:method:: src1() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: dstSelIndex() -> _ods_ir .. py:function:: cvt_scalef32_pk_fp4_f32(res: _ods_ir, old_vdst: _ods_ir[_ods_ir], src0: _ods_ir[_ods_ir], src1: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], dst_sel_index: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32PkFp8Bf16Op(res: _ods_ir, oldVdst: _ods_ir[_ods_ir], src0: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], dstLoHiSel: Union[bool, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert two bf16 values in ``src0`` to two fp8 bytes, dividing by the exponent in ``scale``. The bytes are packed into a 16-bit value which is inserted into ``oldVdst`` at the ``dstLoHiSel`` position, with the entire updated vector being returned. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk.fp8.bf16' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: oldVdst() -> _ods_ir[_ods_ir] .. py:method:: src0() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: dstLoHiSel() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32PkFp8Bf16OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtScaleF32PkFp8Bf16OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk.fp8.bf16' .. py:method:: oldVdst() -> _ods_ir[_ods_ir] .. py:method:: src0() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: dstLoHiSel() -> _ods_ir .. py:function:: cvt_scalef32_pk_fp8_bf16(res: _ods_ir, old_vdst: _ods_ir[_ods_ir], src0: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], dst_lo_hi_sel: Union[bool, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32PkFp8F16Op(res: _ods_ir, oldVdst: _ods_ir[_ods_ir], src0: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], dstLoHiSel: Union[bool, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert two f16 values in ``src0`` to two fp8 bytes, dividing by the exponent in ``scale``. The bytes are packed into a 16-bit value which is inserted into ``oldVdst`` at the ``dstLoHiSel`` position, with the entire updated vector being returned. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk.fp8.f16' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: oldVdst() -> _ods_ir[_ods_ir] .. py:method:: src0() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: dstLoHiSel() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32PkFp8F16OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtScaleF32PkFp8F16OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk.fp8.f16' .. py:method:: oldVdst() -> _ods_ir[_ods_ir] .. py:method:: src0() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: dstLoHiSel() -> _ods_ir .. py:function:: cvt_scalef32_pk_fp8_f16(res: _ods_ir, old_vdst: _ods_ir[_ods_ir], src0: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], dst_lo_hi_sel: Union[bool, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32PkFp8F32Op(res: _ods_ir, oldVdst: _ods_ir[_ods_ir], src0: _ods_ir[_ods_ir], src1: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], dstLoHiSel: Union[bool, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert two f32 values in ``src0`` and ``src1`` to two fp8 bytes, dividing by the exponent in ``scale``. The bytes are packed into a 16-bit value which is inserted into ``oldVdst`` at the ``dstLoHiSel`` position, with the entire updated vector being returned. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk.fp8.f32' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: oldVdst() -> _ods_ir[_ods_ir] .. py:method:: src0() -> _ods_ir[_ods_ir] .. py:method:: src1() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: dstLoHiSel() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32PkFp8F32OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtScaleF32PkFp8F32OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.pk.fp8.f32' .. py:method:: oldVdst() -> _ods_ir[_ods_ir] .. py:method:: src0() -> _ods_ir[_ods_ir] .. py:method:: src1() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: dstLoHiSel() -> _ods_ir .. py:function:: cvt_scalef32_pk_fp8_f32(res: _ods_ir, old_vdst: _ods_ir[_ods_ir], src0: _ods_ir[_ods_ir], src1: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], dst_lo_hi_sel: Union[bool, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32SrBf8BF16Op(res: _ods_ir, oldVdst: _ods_ir[_ods_ir], src0: _ods_ir, seed: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], dstSelIndex: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert a bf16 value in ``src0`` to a bf8 bytes, dividing by the exponent in ``scale`` and using ``seed`` for stochiastic rounding. Place the resulting byte in the ``dstSelIndex``th bit of ``oldVdst`` and return the entire packed vector, which is stored as an ``i32``. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.sr.bf8.bf16' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: oldVdst() -> _ods_ir[_ods_ir] .. py:method:: src0() -> _ods_ir .. py:method:: seed() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: dstSelIndex() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32SrBf8BF16OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtScaleF32SrBf8BF16OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.sr.bf8.bf16' .. py:method:: oldVdst() -> _ods_ir[_ods_ir] .. py:method:: src0() -> _ods_ir .. py:method:: seed() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: dstSelIndex() -> _ods_ir .. py:function:: cvt_scalef32_sr_bf8_bf16(res: _ods_ir, old_vdst: _ods_ir[_ods_ir], src0: _ods_ir, seed: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], dst_sel_index: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32SrBf8F16Op(res: _ods_ir, oldVdst: _ods_ir[_ods_ir], src0: _ods_ir[_ods_ir], seed: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], dstSelIndex: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert a f16 value in ``src0`` to a bf8 bytes, dividing by the exponent in ``scale`` and using ``seed`` for stochiastic rounding. Place the resulting byte in the ``dstSelIndex``th bit of ``oldVdst`` and return the entire packed vector, which is stored as an ``i32``. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.sr.bf8.f16' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: oldVdst() -> _ods_ir[_ods_ir] .. py:method:: src0() -> _ods_ir[_ods_ir] .. py:method:: seed() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: dstSelIndex() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32SrBf8F16OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtScaleF32SrBf8F16OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.sr.bf8.f16' .. py:method:: oldVdst() -> _ods_ir[_ods_ir] .. py:method:: src0() -> _ods_ir[_ods_ir] .. py:method:: seed() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: dstSelIndex() -> _ods_ir .. py:function:: cvt_scalef32_sr_bf8_f16(res: _ods_ir, old_vdst: _ods_ir[_ods_ir], src0: _ods_ir[_ods_ir], seed: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], dst_sel_index: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32SrBf8F32Op(res: _ods_ir, oldVdst: _ods_ir[_ods_ir], src0: _ods_ir[_ods_ir], seed: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], dstSelIndex: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert a f32 value in ``src0`` to a bf8 bytes, dividing by the exponent in ``scale`` and using ``seed`` for stochiastic rounding. Place the resulting byte in the ``dstSelIndex``th bit of ``oldVdst`` and return the entire packed vector, which is stored as an ``i32``. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.sr.bf8.f32' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: oldVdst() -> _ods_ir[_ods_ir] .. py:method:: src0() -> _ods_ir[_ods_ir] .. py:method:: seed() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: dstSelIndex() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32SrBf8F32OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtScaleF32SrBf8F32OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.sr.bf8.f32' .. py:method:: oldVdst() -> _ods_ir[_ods_ir] .. py:method:: src0() -> _ods_ir[_ods_ir] .. py:method:: seed() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: dstSelIndex() -> _ods_ir .. py:function:: cvt_scalef32_sr_bf8_f32(res: _ods_ir, old_vdst: _ods_ir[_ods_ir], src0: _ods_ir[_ods_ir], seed: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], dst_sel_index: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32SrFp8BF16Op(res: _ods_ir, oldVdst: _ods_ir[_ods_ir], src0: _ods_ir, seed: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], dstSelIndex: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert a bf16 value in ``src0`` to a fp8 bytes, dividing by the exponent in ``scale`` and using ``seed`` for stochiastic rounding. Place the resulting byte in the ``dstSelIndex``th bit of ``oldVdst`` and return the entire packed vector, which is stored as an ``i32``. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.sr.fp8.bf16' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: oldVdst() -> _ods_ir[_ods_ir] .. py:method:: src0() -> _ods_ir .. py:method:: seed() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: dstSelIndex() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32SrFp8BF16OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtScaleF32SrFp8BF16OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.sr.fp8.bf16' .. py:method:: oldVdst() -> _ods_ir[_ods_ir] .. py:method:: src0() -> _ods_ir .. py:method:: seed() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: dstSelIndex() -> _ods_ir .. py:function:: cvt_scalef32_sr_fp8_bf16(res: _ods_ir, old_vdst: _ods_ir[_ods_ir], src0: _ods_ir, seed: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], dst_sel_index: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32SrFp8F16Op(res: _ods_ir, oldVdst: _ods_ir[_ods_ir], src0: _ods_ir[_ods_ir], seed: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], dstSelIndex: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert a f16 value in ``src0`` to a fp8 bytes, dividing by the exponent in ``scale`` and using ``seed`` for stochiastic rounding. Place the resulting byte in the ``dstSelIndex``th bit of ``oldVdst`` and return the entire packed vector, which is stored as an ``i32``. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.sr.fp8.f16' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: oldVdst() -> _ods_ir[_ods_ir] .. py:method:: src0() -> _ods_ir[_ods_ir] .. py:method:: seed() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: dstSelIndex() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32SrFp8F16OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtScaleF32SrFp8F16OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.sr.fp8.f16' .. py:method:: oldVdst() -> _ods_ir[_ods_ir] .. py:method:: src0() -> _ods_ir[_ods_ir] .. py:method:: seed() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: dstSelIndex() -> _ods_ir .. py:function:: cvt_scalef32_sr_fp8_f16(res: _ods_ir, old_vdst: _ods_ir[_ods_ir], src0: _ods_ir[_ods_ir], seed: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], dst_sel_index: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32SrFp8F32Op(res: _ods_ir, oldVdst: _ods_ir[_ods_ir], src0: _ods_ir[_ods_ir], seed: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], dstSelIndex: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert a f32 value in ``src0`` to a fp8 bytes, dividing by the exponent in ``scale`` and using ``seed`` for stochiastic rounding. Place the resulting byte in the ``dstSelIndex``th bit of ``oldVdst`` and return the entire packed vector, which is stored as an ``i32``. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.sr.fp8.f32' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: oldVdst() -> _ods_ir[_ods_ir] .. py:method:: src0() -> _ods_ir[_ods_ir] .. py:method:: seed() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: dstSelIndex() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32SrFp8F32OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtScaleF32SrFp8F32OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.sr.fp8.f32' .. py:method:: oldVdst() -> _ods_ir[_ods_ir] .. py:method:: src0() -> _ods_ir[_ods_ir] .. py:method:: seed() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: dstSelIndex() -> _ods_ir .. py:function:: cvt_scalef32_sr_fp8_f32(res: _ods_ir, old_vdst: _ods_ir[_ods_ir], src0: _ods_ir[_ods_ir], seed: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], dst_sel_index: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32SrPk8Bf8Bf16Op(res: _ods_ir, src: _ods_ir[_ods_ir], seed: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert 8 packed bf16 values to packed bf8, multiplying by the exponent part of ``scale`` before doing so and apply stochastic rounding. This op is for gfx1250+ arch. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.sr.pk8.bf8.bf16' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: seed() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32SrPk8Bf8Bf16OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtScaleF32SrPk8Bf8Bf16OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.sr.pk8.bf8.bf16' .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: seed() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:function:: cvt_scalef32_sr_pk8_bf8_bf16(res: _ods_ir, src: _ods_ir[_ods_ir], seed: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32SrPk8Bf8F16Op(res: _ods_ir, src: _ods_ir[_ods_ir], seed: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert 8 packed f16 values to packed bf8, multiplying by the exponent part of ``scale`` before doing so and apply stochastic rounding. This op is for gfx1250+ arch. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.sr.pk8.bf8.f16' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: seed() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32SrPk8Bf8F16OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtScaleF32SrPk8Bf8F16OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.sr.pk8.bf8.f16' .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: seed() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:function:: cvt_scalef32_sr_pk8_bf8_f16(res: _ods_ir, src: _ods_ir[_ods_ir], seed: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32SrPk8Bf8F32Op(res: _ods_ir, src: _ods_ir[_ods_ir], seed: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert 8 packed f32 values to packed bf8, multiplying by the exponent part of ``scale`` before doing so and apply stochastic rounding. This op is for gfx1250+ arch. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.sr.pk8.bf8.f32' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: seed() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32SrPk8Bf8F32OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtScaleF32SrPk8Bf8F32OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.sr.pk8.bf8.f32' .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: seed() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:function:: cvt_scalef32_sr_pk8_bf8_f32(res: _ods_ir, src: _ods_ir[_ods_ir], seed: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32SrPk8Fp4Bf16Op(res: _ods_ir, src: _ods_ir[_ods_ir], seed: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert 8 packed bf16 values to packed fp4, multiplying by the exponent part of ``scale`` before doing so and apply stochastic rounding. This op is for gfx1250+ arch. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.sr.pk8.fp4.bf16' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: seed() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32SrPk8Fp4Bf16OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtScaleF32SrPk8Fp4Bf16OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.sr.pk8.fp4.bf16' .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: seed() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:function:: cvt_scalef32_sr_pk8_fp4_bf16(res: _ods_ir, src: _ods_ir[_ods_ir], seed: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32SrPk8Fp4F16Op(res: _ods_ir, src: _ods_ir[_ods_ir], seed: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert 8 packed f16 values to packed fp4, multiplying by the exponent part of ``scale`` before doing so and apply stochastic rounding. This op is for gfx1250+ arch. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.sr.pk8.fp4.f16' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: seed() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32SrPk8Fp4F16OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtScaleF32SrPk8Fp4F16OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.sr.pk8.fp4.f16' .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: seed() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:function:: cvt_scalef32_sr_pk8_fp4_f16(res: _ods_ir, src: _ods_ir[_ods_ir], seed: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32SrPk8Fp4F32Op(res: _ods_ir, src: _ods_ir[_ods_ir], seed: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert 8 packed f32 values to packed fp4, multiplying by the exponent part of ``scale`` before doing so and apply stochastic rounding. This op is for gfx1250+ arch. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.sr.pk8.fp4.f32' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: seed() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32SrPk8Fp4F32OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtScaleF32SrPk8Fp4F32OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.sr.pk8.fp4.f32' .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: seed() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:function:: cvt_scalef32_sr_pk8_fp4_f32(res: _ods_ir, src: _ods_ir[_ods_ir], seed: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32SrPk8Fp8Bf16Op(res: _ods_ir, src: _ods_ir[_ods_ir], seed: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert 8 packed bf16 values to packed fp8, multiplying by the exponent part of ``scale`` before doing so and apply stochastic rounding. This op is for gfx1250+ arch. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.sr.pk8.fp8.bf16' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: seed() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32SrPk8Fp8Bf16OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtScaleF32SrPk8Fp8Bf16OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.sr.pk8.fp8.bf16' .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: seed() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:function:: cvt_scalef32_sr_pk8_fp8_bf16(res: _ods_ir, src: _ods_ir[_ods_ir], seed: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32SrPk8Fp8F16Op(res: _ods_ir, src: _ods_ir[_ods_ir], seed: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert 8 packed f16 values to packed fp8, multiplying by the exponent part of ``scale`` before doing so and apply stochastic rounding. This op is for gfx1250+ arch. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.sr.pk8.fp8.f16' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: seed() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32SrPk8Fp8F16OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtScaleF32SrPk8Fp8F16OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.sr.pk8.fp8.f16' .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: seed() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:function:: cvt_scalef32_sr_pk8_fp8_f16(res: _ods_ir, src: _ods_ir[_ods_ir], seed: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32SrPk8Fp8F32Op(res: _ods_ir, src: _ods_ir[_ods_ir], seed: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert 8 packed f32 values to packed fp8, multiplying by the exponent part of ``scale`` before doing so and apply stochastic rounding. This op is for gfx1250+ arch. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.sr.pk8.fp8.f32' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: seed() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32SrPk8Fp8F32OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtScaleF32SrPk8Fp8F32OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.sr.pk8.fp8.f32' .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: seed() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:function:: cvt_scalef32_sr_pk8_fp8_f32(res: _ods_ir, src: _ods_ir[_ods_ir], seed: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32SrPk16Bf6Bf16Op(res: _ods_ir, src: _ods_ir[_ods_ir], seed: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert 8 packed bf16 values to packed bf6, multiplying by the exponent part of ``scale`` before doing so and apply stochastic rounding. This op is for gfx1250+ arch. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.sr.pk16.bf6.bf16' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: seed() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32SrPk16Bf6Bf16OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtScaleF32SrPk16Bf6Bf16OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.sr.pk16.bf6.bf16' .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: seed() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:function:: cvt_scalef32_sr_pk16_bf6_bf16(res: _ods_ir, src: _ods_ir[_ods_ir], seed: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32SrPk16Bf6F16Op(res: _ods_ir, src: _ods_ir[_ods_ir], seed: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert 8 packed f16 values to packed bf6, multiplying by the exponent part of ``scale`` before doing so and apply stochastic rounding. This op is for gfx1250+ arch. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.sr.pk16.bf6.f16' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: seed() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32SrPk16Bf6F16OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtScaleF32SrPk16Bf6F16OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.sr.pk16.bf6.f16' .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: seed() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:function:: cvt_scalef32_sr_pk16_bf6_f16(res: _ods_ir, src: _ods_ir[_ods_ir], seed: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32SrPk16Bf6F32Op(res: _ods_ir, src: _ods_ir[_ods_ir], seed: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert 8 packed f32 values to packed bf6, multiplying by the exponent part of ``scale`` before doing so and apply stochastic rounding. This op is for gfx1250+ arch. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.sr.pk16.bf6.f32' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: seed() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32SrPk16Bf6F32OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtScaleF32SrPk16Bf6F32OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.sr.pk16.bf6.f32' .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: seed() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:function:: cvt_scalef32_sr_pk16_bf6_f32(res: _ods_ir, src: _ods_ir[_ods_ir], seed: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32SrPk16Fp6Bf16Op(res: _ods_ir, src: _ods_ir[_ods_ir], seed: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert 8 packed bf16 values to packed fp6, multiplying by the exponent part of ``scale`` before doing so and apply stochastic rounding. This op is for gfx1250+ arch. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.sr.pk16.fp6.bf16' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: seed() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32SrPk16Fp6Bf16OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtScaleF32SrPk16Fp6Bf16OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.sr.pk16.fp6.bf16' .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: seed() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:function:: cvt_scalef32_sr_pk16_fp6_bf16(res: _ods_ir, src: _ods_ir[_ods_ir], seed: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32SrPk16Fp6F16Op(res: _ods_ir, src: _ods_ir[_ods_ir], seed: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert 8 packed f16 values to packed fp6, multiplying by the exponent part of ``scale`` before doing so and apply stochastic rounding. This op is for gfx1250+ arch. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.sr.pk16.fp6.f16' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: seed() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32SrPk16Fp6F16OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtScaleF32SrPk16Fp6F16OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.sr.pk16.fp6.f16' .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: seed() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:function:: cvt_scalef32_sr_pk16_fp6_f16(res: _ods_ir, src: _ods_ir[_ods_ir], seed: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32SrPk16Fp6F32Op(res: _ods_ir, src: _ods_ir[_ods_ir], seed: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert 8 packed f32 values to packed fp6, multiplying by the exponent part of ``scale`` before doing so and apply stochastic rounding. This op is for gfx1250+ arch. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.sr.pk16.fp6.f32' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: seed() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32SrPk16Fp6F32OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtScaleF32SrPk16Fp6F32OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.sr.pk16.fp6.f32' .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: seed() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:function:: cvt_scalef32_sr_pk16_fp6_f32(res: _ods_ir, src: _ods_ir[_ods_ir], seed: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32SrPk32Bf6Bf16Op(res: _ods_ir, src: _ods_ir[_ods_ir], seed: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert 32 packed bf16 values to packed bf6, dividing by the exponent part of ``scale`` before doing so and applying random rounding derived from ``seed``. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.sr.pk32.bf6.bf16' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: seed() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32SrPk32Bf6Bf16OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtScaleF32SrPk32Bf6Bf16OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.sr.pk32.bf6.bf16' .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: seed() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:function:: cvt_scalef32_sr_pk32_bf6_bf16(res: _ods_ir, src: _ods_ir[_ods_ir], seed: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32SrPk32Bf6F16Op(res: _ods_ir, src: _ods_ir[_ods_ir], seed: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert 32 packed f16 values to packed bf6, dividing by the exponent part of ``scale`` before doing so and applying random rounding derived from ``seed``. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.sr.pk32.bf6.f16' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: seed() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32SrPk32Bf6F16OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtScaleF32SrPk32Bf6F16OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.sr.pk32.bf6.f16' .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: seed() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:function:: cvt_scalef32_sr_pk32_bf6_f16(res: _ods_ir, src: _ods_ir[_ods_ir], seed: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32SrPk32Bf6F32Op(res: _ods_ir, src: _ods_ir[_ods_ir], seed: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert 32 packed f32 values to packed bf6, dividing by the exponent part of ``scale`` before doing so and applying random rounding derived from ``seed``. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.sr.pk32.bf6.f32' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: seed() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32SrPk32Bf6F32OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtScaleF32SrPk32Bf6F32OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.sr.pk32.bf6.f32' .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: seed() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:function:: cvt_scalef32_sr_pk32_bf6_f32(res: _ods_ir, src: _ods_ir[_ods_ir], seed: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32SrPk32Fp6Bf16Op(res: _ods_ir, src: _ods_ir[_ods_ir], seed: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert 32 packed bf16 values to packed fp6, dividing by the exponent part of ``scale`` before doing so and applying random rounding derived from ``seed``. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.sr.pk32.fp6.bf16' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: seed() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32SrPk32Fp6Bf16OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtScaleF32SrPk32Fp6Bf16OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.sr.pk32.fp6.bf16' .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: seed() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:function:: cvt_scalef32_sr_pk32_fp6_bf16(res: _ods_ir, src: _ods_ir[_ods_ir], seed: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32SrPk32Fp6F16Op(res: _ods_ir, src: _ods_ir[_ods_ir], seed: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert 32 packed f16 values to packed fp6, dividing by the exponent part of ``scale`` before doing so and applying random rounding derived from ``seed``. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.sr.pk32.fp6.f16' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: seed() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32SrPk32Fp6F16OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtScaleF32SrPk32Fp6F16OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.sr.pk32.fp6.f16' .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: seed() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:function:: cvt_scalef32_sr_pk32_fp6_f16(res: _ods_ir, src: _ods_ir[_ods_ir], seed: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32SrPk32Fp6F32Op(res: _ods_ir, src: _ods_ir[_ods_ir], seed: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert 32 packed f32 values to packed fp6, dividing by the exponent part of ``scale`` before doing so and applying random rounding derived from ``seed``. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.sr.pk32.fp6.f32' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: seed() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32SrPk32Fp6F32OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtScaleF32SrPk32Fp6F32OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.sr.pk32.fp6.f32' .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: seed() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:function:: cvt_scalef32_sr_pk32_fp6_f32(res: _ods_ir, src: _ods_ir[_ods_ir], seed: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32SrPkFp4Bf16Op(res: _ods_ir, oldVdst: _ods_ir[_ods_ir], src: _ods_ir[_ods_ir], seed: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], dstSelIndex: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert two packed bf16 values to packed fp4, dividing by the exponent part of ``scale`` before doing so and using ``seed`` as the random seed for stochiastic rounding. The two scaled values are packed (little-endian) into a byte. That byte is used to update the ``dstSelIndex``th byte of ``oldVdst``, which is returned in its entirity. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.sr.pk.fp4.bf16' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: oldVdst() -> _ods_ir[_ods_ir] .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: seed() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: dstSelIndex() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32SrPkFp4Bf16OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtScaleF32SrPkFp4Bf16OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.sr.pk.fp4.bf16' .. py:method:: oldVdst() -> _ods_ir[_ods_ir] .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: seed() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: dstSelIndex() -> _ods_ir .. py:function:: cvt_scalef32_sr_pk_fp4_bf16(res: _ods_ir, old_vdst: _ods_ir[_ods_ir], src: _ods_ir[_ods_ir], seed: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], dst_sel_index: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32SrPkFp4F16Op(res: _ods_ir, oldVdst: _ods_ir[_ods_ir], src: _ods_ir[_ods_ir], seed: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], dstSelIndex: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert two packed f16 values to packed fp4, dividing by the exponent part of ``scale`` before doing so and using ``seed`` as the random seed for stochiastic rounding. The two scaled values are packed (little-endian) into a byte. That byte is used to update the ``dstSelIndex``th byte of ``oldVdst``, which is returned in its entirity. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.sr.pk.fp4.f16' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: oldVdst() -> _ods_ir[_ods_ir] .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: seed() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: dstSelIndex() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32SrPkFp4F16OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtScaleF32SrPkFp4F16OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.sr.pk.fp4.f16' .. py:method:: oldVdst() -> _ods_ir[_ods_ir] .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: seed() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: dstSelIndex() -> _ods_ir .. py:function:: cvt_scalef32_sr_pk_fp4_f16(res: _ods_ir, old_vdst: _ods_ir[_ods_ir], src: _ods_ir[_ods_ir], seed: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], dst_sel_index: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32SrPkFp4F32Op(res: _ods_ir, oldVdst: _ods_ir[_ods_ir], src: _ods_ir[_ods_ir], seed: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], dstSelIndex: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert two packed f32 values to packed fp4, dividing by the exponent part of ``scale`` before doing so and using ``seed`` as the random seed for stochiastic rounding. The two scaled values are packed (little-endian) into a byte. That byte is used to update the ``dstSelIndex``th byte of ``oldVdst``, which is returned in its entirity. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.sr.pk.fp4.f32' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: oldVdst() -> _ods_ir[_ods_ir] .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: seed() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: dstSelIndex() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF32SrPkFp4F32OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtScaleF32SrPkFp4F32OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.sr.pk.fp4.f32' .. py:method:: oldVdst() -> _ods_ir[_ods_ir] .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: seed() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: dstSelIndex() -> _ods_ir .. py:function:: cvt_scalef32_sr_pk_fp4_f32(res: _ods_ir, old_vdst: _ods_ir[_ods_ir], src: _ods_ir[_ods_ir], seed: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], dst_sel_index: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF322xPk16Bf6F32Op(res: _ods_ir, src0: _ods_ir[_ods_ir], src1: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert 32 single-precision float values, packed into two length-16 vectors that will be logically concanenated, to packed bf6, dividing by the exponent part of ``scale`` before doing so. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.2xpk16.bf6.f32' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: src0() -> _ods_ir[_ods_ir] .. py:method:: src1() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF322xPk16Bf6F32OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtScaleF322xPk16Bf6F32OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.2xpk16.bf6.f32' .. py:method:: src0() -> _ods_ir[_ods_ir] .. py:method:: src1() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:function:: cvt_scalef32_2xpk16_bf6_f32(res: _ods_ir, src0: _ods_ir[_ods_ir], src1: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF322xPk16Fp6F32Op(res: _ods_ir, src0: _ods_ir[_ods_ir], src1: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert 32 single-precision float values, packed into two length-16 vectors that will be logically concanenated, to packed fp6, dividing by the exponent part of ``scale`` before doing so. .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.2xpk16.fp6.f32' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: src0() -> _ods_ir[_ods_ir] .. py:method:: src1() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: CvtScaleF322xPk16Fp6F32OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtScaleF322xPk16Fp6F32OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.scalef32.2xpk16.fp6.f32' .. py:method:: src0() -> _ods_ir[_ods_ir] .. py:method:: src1() -> _ods_ir[_ods_ir] .. py:method:: scale() -> _ods_ir[_ods_ir] .. py:function:: cvt_scalef32_2xpk16_fp6_f32(res: _ods_ir, src0: _ods_ir[_ods_ir], src1: _ods_ir[_ods_ir], scale: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: CvtSrBf8F32Op(res: _ods_ir, srcA: _ods_ir[_ods_ir], srcB: _ods_ir[_ods_ir], old: _ods_ir[_ods_ir], byteSel: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert ``srcA`` to bf8, adding the rounding factor from ``srcB``, and store into the ``byteSel``th byte of ``old``, preserving the others. Example: .. code:: mlir // Stochastic rounding convert f32 to bf8 in byte 2 of old. %0 = rocdl.cvt.sr.bf8.f32 %val, %stoch -> %old[2] : i32 .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.sr.bf8.f32' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: srcA() -> _ods_ir[_ods_ir] .. py:method:: srcB() -> _ods_ir[_ods_ir] .. py:method:: old() -> _ods_ir[_ods_ir] .. py:method:: byteSel() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: CvtSrBf8F32OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtSrBf8F32OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.sr.bf8.f32' .. py:method:: srcA() -> _ods_ir[_ods_ir] .. py:method:: srcB() -> _ods_ir[_ods_ir] .. py:method:: old() -> _ods_ir[_ods_ir] .. py:method:: byteSel() -> _ods_ir .. py:function:: cvt_sr_bf8_f32(res: _ods_ir, src_a: _ods_ir[_ods_ir], src_b: _ods_ir[_ods_ir], old: _ods_ir[_ods_ir], byte_sel: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: CvtSrFp8F32Op(res: _ods_ir, srcA: _ods_ir[_ods_ir], srcB: _ods_ir[_ods_ir], old: _ods_ir[_ods_ir], byteSel: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Convert ``srcA`` to fp8, adding the rounding factor from ``srcB``, and store into the ``byteSel``th byte of ``old``, preserving the others. Example: .. code:: mlir // Stochastic rounding convert f32 to fp8 in byte 3 of old. %0 = rocdl.cvt.sr.fp8.f32 %val, %stoch -> %old[3] : i32 .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.sr.fp8.f32' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: srcA() -> _ods_ir[_ods_ir] .. py:method:: srcB() -> _ods_ir[_ods_ir] .. py:method:: old() -> _ods_ir[_ods_ir] .. py:method:: byteSel() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: CvtSrFp8F32OpAdaptor(operands: list[Value], attributes: OpAttributeMap) CvtSrFp8F32OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.cvt.sr.fp8.f32' .. py:method:: srcA() -> _ods_ir[_ods_ir] .. py:method:: srcB() -> _ods_ir[_ods_ir] .. py:method:: old() -> _ods_ir[_ods_ir] .. py:method:: byteSel() -> _ods_ir .. py:function:: cvt_sr_fp8_f32(res: _ods_ir, src_a: _ods_ir[_ods_ir], src_b: _ods_ir[_ods_ir], old: _ods_ir[_ods_ir], byte_sel: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: DPPUpdateOp(res: _ods_ir, old: _ods_ir, src: _ods_ir, dppCtrl: Union[int, _ods_ir], rowMask: Union[int, _ods_ir], bankMask: Union[int, _ods_ir], boundCtrl: Union[bool, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.update.dpp' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: old() -> _ods_ir .. py:method:: src() -> _ods_ir .. py:method:: dppCtrl() -> _ods_ir .. py:method:: rowMask() -> _ods_ir .. py:method:: bankMask() -> _ods_ir .. py:method:: boundCtrl() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: DPPUpdateOpAdaptor(operands: list[Value], attributes: OpAttributeMap) DPPUpdateOpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.update.dpp' .. py:method:: old() -> _ods_ir .. py:method:: src() -> _ods_ir .. py:method:: dppCtrl() -> _ods_ir .. py:method:: rowMask() -> _ods_ir .. py:method:: bankMask() -> _ods_ir .. py:method:: boundCtrl() -> _ods_ir .. py:function:: update_dpp(res: _ods_ir, old: _ods_ir, src: _ods_ir, dpp_ctrl: Union[int, _ods_ir], row_mask: Union[int, _ods_ir], bank_mask: Union[int, _ods_ir], bound_ctrl: Union[bool, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: DsAtomicAsyncBarrierArriveOp(barrierPtr: _ods_ir, *, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Waits on a given DS barrier and decrements pending count by -1. Stays in order with ASYNC loads to LDS, and uses ASYNCcnt to track its completion. Available on gfx1250+. Example: .. code:: mlir // Async atomic barrier arrive (fire-and-forget). rocdl.ds.atomic.async.barrier.arrive.b64 %ptr : !llvm.ptr<3> .. py:attribute:: OPERATION_NAME :value: 'rocdl.ds.atomic.async.barrier.arrive.b64' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: barrierPtr() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:class:: DsAtomicAsyncBarrierArriveOpAdaptor(operands: list[Value], attributes: OpAttributeMap) DsAtomicAsyncBarrierArriveOpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.ds.atomic.async.barrier.arrive.b64' .. py:method:: barrierPtr() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:function:: ds_atomic_async_barrier_arrive_b64(barrier_ptr: _ods_ir, *, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> DsAtomicAsyncBarrierArriveOp .. py:class:: DsAtomicBarrierArriveRtnOp(res: _ods_ir, barrierPtr: _ods_ir, val: _ods_ir[_ods_ir], *, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Waits on a given DS barrier and decrements its pending count by a given value. Note, the barrier state is given as a 64-bit structure containing pending count, phase and init count. The op returns the old barrier state. The op is executed as an ordinary LDS operations and it is ordered with other LDS operations. Thus, check DSCNT to determine when this instruction has executed. Available on gfx1250+. Example: .. code:: mlir // Atomic barrier arrive with return of old barrier state. %res = rocdl.ds.atomic.barrier.arrive.rtn.b64 %ptr, %val : !llvm.ptr<3>, i64 -> i64 .. py:attribute:: OPERATION_NAME :value: 'rocdl.ds.atomic.barrier.arrive.rtn.b64' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: barrierPtr() -> _ods_ir .. py:method:: val() -> _ods_ir[_ods_ir] .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: DsAtomicBarrierArriveRtnOpAdaptor(operands: list[Value], attributes: OpAttributeMap) DsAtomicBarrierArriveRtnOpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.ds.atomic.barrier.arrive.rtn.b64' .. py:method:: barrierPtr() -> _ods_ir .. py:method:: val() -> _ods_ir[_ods_ir] .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:function:: ds_atomic_barrier_arrive_rtn_b64(res: _ods_ir, barrier_ptr: _ods_ir, val: _ods_ir[_ods_ir], *, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: DsBpermuteOp(res: _ods_ir, index: _ods_ir[_ods_ir], src: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Perform a backward permute (pull) operation across lanes using DS/LDS permute hardware. Each lane reads the value of ``src`` from the lane whose byte address is given by ``index`` (i.e. lane id = ``index / 4``). This is “backward” (pull) in contrast to ``ds_permute_b32``, which is “forward” (push/scatter). Example: .. code:: mlir // Backward permute across lanes (pull from selected lane). %0 = rocdl.ds_bpermute %index, %src : (i32, i32) -> i32 .. py:attribute:: OPERATION_NAME :value: 'rocdl.ds_bpermute' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: DsBpermuteOpAdaptor(operands: list[Value], attributes: OpAttributeMap) DsBpermuteOpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.ds_bpermute' .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: src() -> _ods_ir[_ods_ir] .. py:function:: ds_bpermute(res: _ods_ir, index: _ods_ir[_ods_ir], src: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: DsLoadTr4_B64(res: _ods_ir, ptr: _ods_ir, *, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Load a matrix of 4-bit data from the ds memory, transpose data between row-major and column-major order, and store the result into a 64-bit vector register. Available in gfx1250+. Example (concrete mnemonics depend on address space and element size): .. code:: mlir // 64-bit transpose load from global memory. %0 = rocdl.global.load.tr4.b64 %ptr : !llvm.ptr<1> -> vector<2xi32> // 128-bit transpose load from global memory with f16 result. %1 = rocdl.global.load.tr.b128 %ptr : !llvm.ptr<1> -> vector<8xf16> // 64-bit transpose load from LDS. %2 = rocdl.ds.load.tr4.b64 %ptr : !llvm.ptr<3> -> vector<2xi32> // 128-bit transpose load from LDS with bf16 result. %3 = rocdl.ds.load.tr16.b128 %ptr : !llvm.ptr<3> -> vector<8xbf16> .. py:attribute:: OPERATION_NAME :value: 'rocdl.ds.load.tr4.b64' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: ptr() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:method:: res() -> _ods_ir .. py:class:: DsLoadTr4_B64Adaptor(operands: list[Value], attributes: OpAttributeMap) DsLoadTr4_B64Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.ds.load.tr4.b64' .. py:method:: ptr() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:function:: ds_load_tr4_b64(res: _ods_ir, ptr: _ods_ir, *, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: DsLoadTr6_B96(res: _ods_ir, ptr: _ods_ir, *, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Load a matrix of 6-bit data from the ds memory, transpose data between row-major and column-major order, and store the result into a 96-bit vector register. Available in gfx1250+. Example (concrete mnemonics depend on address space and element size): .. code:: mlir // 64-bit transpose load from global memory. %0 = rocdl.global.load.tr4.b64 %ptr : !llvm.ptr<1> -> vector<2xi32> // 128-bit transpose load from global memory with f16 result. %1 = rocdl.global.load.tr.b128 %ptr : !llvm.ptr<1> -> vector<8xf16> // 64-bit transpose load from LDS. %2 = rocdl.ds.load.tr4.b64 %ptr : !llvm.ptr<3> -> vector<2xi32> // 128-bit transpose load from LDS with bf16 result. %3 = rocdl.ds.load.tr16.b128 %ptr : !llvm.ptr<3> -> vector<8xbf16> .. py:attribute:: OPERATION_NAME :value: 'rocdl.ds.load.tr6.b96' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: ptr() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:method:: res() -> _ods_ir .. py:class:: DsLoadTr6_B96Adaptor(operands: list[Value], attributes: OpAttributeMap) DsLoadTr6_B96Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.ds.load.tr6.b96' .. py:method:: ptr() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:function:: ds_load_tr6_b96(res: _ods_ir, ptr: _ods_ir, *, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: DsLoadTr8_B64(res: _ods_ir, ptr: _ods_ir, *, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Load a matrix of 8-bit data from the ds memory, transpose data between row-major and column-major order, and store the result into a 64-bit vector register. Available in gfx1250+. Example (concrete mnemonics depend on address space and element size): .. code:: mlir // 64-bit transpose load from global memory. %0 = rocdl.global.load.tr4.b64 %ptr : !llvm.ptr<1> -> vector<2xi32> // 128-bit transpose load from global memory with f16 result. %1 = rocdl.global.load.tr.b128 %ptr : !llvm.ptr<1> -> vector<8xf16> // 64-bit transpose load from LDS. %2 = rocdl.ds.load.tr4.b64 %ptr : !llvm.ptr<3> -> vector<2xi32> // 128-bit transpose load from LDS with bf16 result. %3 = rocdl.ds.load.tr16.b128 %ptr : !llvm.ptr<3> -> vector<8xbf16> .. py:attribute:: OPERATION_NAME :value: 'rocdl.ds.load.tr8.b64' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: ptr() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:method:: res() -> _ods_ir .. py:class:: DsLoadTr8_B64Adaptor(operands: list[Value], attributes: OpAttributeMap) DsLoadTr8_B64Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.ds.load.tr8.b64' .. py:method:: ptr() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:function:: ds_load_tr8_b64(res: _ods_ir, ptr: _ods_ir, *, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: DsLoadTr16_B128(res: _ods_ir, ptr: _ods_ir, *, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Load a matrix of 16-bit data from the ds memory, transpose data between row-major and column-major order, and store the result into a 128-bit vector register. Available in gfx1250+. Example (concrete mnemonics depend on address space and element size): .. code:: mlir // 64-bit transpose load from global memory. %0 = rocdl.global.load.tr4.b64 %ptr : !llvm.ptr<1> -> vector<2xi32> // 128-bit transpose load from global memory with f16 result. %1 = rocdl.global.load.tr.b128 %ptr : !llvm.ptr<1> -> vector<8xf16> // 64-bit transpose load from LDS. %2 = rocdl.ds.load.tr4.b64 %ptr : !llvm.ptr<3> -> vector<2xi32> // 128-bit transpose load from LDS with bf16 result. %3 = rocdl.ds.load.tr16.b128 %ptr : !llvm.ptr<3> -> vector<8xbf16> .. py:attribute:: OPERATION_NAME :value: 'rocdl.ds.load.tr16.b128' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: ptr() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:method:: res() -> _ods_ir .. py:class:: DsLoadTr16_B128Adaptor(operands: list[Value], attributes: OpAttributeMap) DsLoadTr16_B128Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.ds.load.tr16.b128' .. py:method:: ptr() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:function:: ds_load_tr16_b128(res: _ods_ir, ptr: _ods_ir, *, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: DsSwizzleOp(res: _ods_ir, src: _ods_ir[_ods_ir], offset: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Perform a data-sharing swizzle operation within a wavefront. The ``offset`` operand encodes the *swizzle pattern* that will be placed in the instruction's ``offset`` field (i.e., the pattern used by ``ds_swizzle_b32``). See https://llvm.org/docs/AMDGPUModifierSyntax.html#swizzle-pattern for how this 16-bit pattern is constructed. Example: .. code:: mlir // Swizzle data within a wavefront. %0 = rocdl.ds_swizzle %src, %offset : (i32, i32) -> i32 .. py:attribute:: OPERATION_NAME :value: 'rocdl.ds_swizzle' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: offset() -> _ods_ir[_ods_ir] .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: DsSwizzleOpAdaptor(operands: list[Value], attributes: OpAttributeMap) DsSwizzleOpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.ds_swizzle' .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: offset() -> _ods_ir[_ods_ir] .. py:function:: ds_swizzle(res: _ods_ir, src: _ods_ir[_ods_ir], offset: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: FMed3Op(res: _ods_ir, src0: _ods_ir, src1: _ods_ir, src2: _ods_ir, *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Computes the median of three floating-point values using the AMDGPU fmed3 intrinsic. This operation is equivalent to ``max(min(a, b), min(max(a, b), c))`` but uses the hardware-accelerated V_MED3_F16/V_MED3_F32 instruction for better performance. The operation supports both scalar and vector floating-point types (f16, f32). Example: .. code:: mlir // Scalar f32 median %result = rocdl.fmed3 %a, %b, %c : f32 // Vector f16 median %result = rocdl.fmed3 %va, %vb, %vc : vector<4xf16> .. py:attribute:: OPERATION_NAME :value: 'rocdl.fmed3' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: src0() -> _ods_ir .. py:method:: src1() -> _ods_ir .. py:method:: src2() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: FMed3OpAdaptor(operands: list[Value], attributes: OpAttributeMap) FMed3OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.fmed3' .. py:method:: src0() -> _ods_ir .. py:method:: src1() -> _ods_ir .. py:method:: src2() -> _ods_ir .. py:function:: fmed3(res: _ods_ir, src0: _ods_ir, src1: _ods_ir, src2: _ods_ir, *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: FlatPrefetchOp(ptr: _ods_ir, *, cachePolicy: Optional[Union[Any, _ods_ir]] = None, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Prefetches 1 byte of data per lane using flat-memory addresses into the WGP-cache or L2-cache. Available on gfx1250+. Example: .. code:: mlir // Prefetch from flat memory into cache. rocdl.flat.prefetch %ptr, 0 : !llvm.ptr .. py:attribute:: OPERATION_NAME :value: 'rocdl.flat.prefetch' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: ptr() -> _ods_ir .. py:method:: cachePolicy() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:class:: FlatPrefetchOpAdaptor(operands: list[Value], attributes: OpAttributeMap) FlatPrefetchOpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.flat.prefetch' .. py:method:: ptr() -> _ods_ir .. py:method:: cachePolicy() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:function:: flat_prefetch(ptr: _ods_ir, *, cache_policy: Optional[Union[Any, _ods_ir]] = None, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> FlatPrefetchOp .. py:class:: GetBarrierStateOp(res: _ods_ir, id: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Available on gfx1200+. Example: .. code:: mlir // Query barrier state by id. %0 = rocdl.s.get.barrier.state id = 1 -> i32 .. py:attribute:: OPERATION_NAME :value: 'rocdl.s.get.barrier.state' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: id() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: GetBarrierStateOpAdaptor(operands: list[Value], attributes: OpAttributeMap) GetBarrierStateOpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.s.get.barrier.state' .. py:method:: id() -> _ods_ir .. py:function:: s_get_barrier_state(res: _ods_ir, id: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: GetNamedBarrierStateOp(res: _ods_ir, ptr: _ods_ir, *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Available on gfx1250+. Example: .. code:: mlir // Query named barrier state by pointer. %0 = rocdl.s.get.named.barrier.state %ptr : !llvm.ptr<3> -> i32 .. py:attribute:: OPERATION_NAME :value: 'rocdl.s.get.named.barrier.state' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: ptr() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: GetNamedBarrierStateOpAdaptor(operands: list[Value], attributes: OpAttributeMap) GetNamedBarrierStateOpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.s.get.named.barrier.state' .. py:method:: ptr() -> _ods_ir .. py:function:: s_get_named_barrier_state(res: _ods_ir, ptr: _ods_ir, *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: GlobalLoadAsyncLDSOp(globalPtr: _ods_ir, ldsPtr: _ods_ir, size: Union[int, _ods_ir], offset: Union[int, _ods_ir], *, aux: Optional[Union[Any, _ods_ir]] = None, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` This operation works identically to ``rocdl.load.async.to.lds`` except that the global pointer argument is limited to pointers in address space 1 (pure global pointers) instead of also allowing fat buffer pointers. Available on gfx9 and gfx10. For the operation introduced in gfx1250, see ``rocdl.global.load.async.to.lds.bN``. Example: .. code:: mlir // Async load from global pointer to LDS (address space 1 only). rocdl.load.async.to.lds %global, %shared, 4, 0, 0 : !llvm.ptr<1>, !llvm.ptr<3> .. py:attribute:: OPERATION_NAME :value: 'rocdl.global.load.async.lds' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: globalPtr() -> _ods_ir .. py:method:: ldsPtr() -> _ods_ir .. py:method:: size() -> _ods_ir .. py:method:: offset() -> _ods_ir .. py:method:: aux() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:class:: GlobalLoadAsyncLDSOpAdaptor(operands: list[Value], attributes: OpAttributeMap) GlobalLoadAsyncLDSOpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.global.load.async.lds' .. py:method:: globalPtr() -> _ods_ir .. py:method:: ldsPtr() -> _ods_ir .. py:method:: size() -> _ods_ir .. py:method:: offset() -> _ods_ir .. py:method:: aux() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:function:: global_load_async_lds(global_ptr: _ods_ir, lds_ptr: _ods_ir, size: Union[int, _ods_ir], offset: Union[int, _ods_ir], *, aux: Optional[Union[Any, _ods_ir]] = None, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> GlobalLoadAsyncLDSOp .. py:class:: GlobalLoadAsyncToLDSB8Op(globalPtr: _ods_ir, ldsPtr: _ods_ir, offset: Union[int, _ods_ir], *, aux: Optional[Union[Any, _ods_ir]] = None, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Asynchronously loads 8 bits of data from a global memory pointer to a Local Data Share (LDS) pointer. Available on gfx1250+. Example: .. code:: mlir // Async 8-bit load from global to LDS. rocdl.global.load.async.to.lds.b8 %src, %dst, 0, 0 : !llvm.ptr<1>, !llvm.ptr<3> .. py:attribute:: OPERATION_NAME :value: 'rocdl.global.load.async.to.lds.b8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: globalPtr() -> _ods_ir .. py:method:: ldsPtr() -> _ods_ir .. py:method:: offset() -> _ods_ir .. py:method:: aux() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:class:: GlobalLoadAsyncToLDSB8OpAdaptor(operands: list[Value], attributes: OpAttributeMap) GlobalLoadAsyncToLDSB8OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.global.load.async.to.lds.b8' .. py:method:: globalPtr() -> _ods_ir .. py:method:: ldsPtr() -> _ods_ir .. py:method:: offset() -> _ods_ir .. py:method:: aux() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:function:: global_load_async_to_lds_b8(global_ptr: _ods_ir, lds_ptr: _ods_ir, offset: Union[int, _ods_ir], *, aux: Optional[Union[Any, _ods_ir]] = None, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> GlobalLoadAsyncToLDSB8Op .. py:class:: GlobalLoadAsyncToLDSB32Op(globalPtr: _ods_ir, ldsPtr: _ods_ir, offset: Union[int, _ods_ir], *, aux: Optional[Union[Any, _ods_ir]] = None, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Asynchronously loads 32 bits of data from a global memory pointer to a Local Data Share (LDS) pointer. Available on gfx1250+. Example: .. code:: mlir // Async 32-bit load from global to LDS. rocdl.global.load.async.to.lds.b32 %src, %dst, 0, 0 : !llvm.ptr<1>, !llvm.ptr<3> .. py:attribute:: OPERATION_NAME :value: 'rocdl.global.load.async.to.lds.b32' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: globalPtr() -> _ods_ir .. py:method:: ldsPtr() -> _ods_ir .. py:method:: offset() -> _ods_ir .. py:method:: aux() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:class:: GlobalLoadAsyncToLDSB32OpAdaptor(operands: list[Value], attributes: OpAttributeMap) GlobalLoadAsyncToLDSB32OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.global.load.async.to.lds.b32' .. py:method:: globalPtr() -> _ods_ir .. py:method:: ldsPtr() -> _ods_ir .. py:method:: offset() -> _ods_ir .. py:method:: aux() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:function:: global_load_async_to_lds_b32(global_ptr: _ods_ir, lds_ptr: _ods_ir, offset: Union[int, _ods_ir], *, aux: Optional[Union[Any, _ods_ir]] = None, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> GlobalLoadAsyncToLDSB32Op .. py:class:: GlobalLoadAsyncToLDSB64Op(globalPtr: _ods_ir, ldsPtr: _ods_ir, offset: Union[int, _ods_ir], *, aux: Optional[Union[Any, _ods_ir]] = None, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Asynchronously loads 64 bits of data from a global memory pointer to a Local Data Share (LDS) pointer. Available on gfx1250+. Example: .. code:: mlir // Async 64-bit load from global to LDS. rocdl.global.load.async.to.lds.b64 %src, %dst, 0, 0 : !llvm.ptr<1>, !llvm.ptr<3> .. py:attribute:: OPERATION_NAME :value: 'rocdl.global.load.async.to.lds.b64' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: globalPtr() -> _ods_ir .. py:method:: ldsPtr() -> _ods_ir .. py:method:: offset() -> _ods_ir .. py:method:: aux() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:class:: GlobalLoadAsyncToLDSB64OpAdaptor(operands: list[Value], attributes: OpAttributeMap) GlobalLoadAsyncToLDSB64OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.global.load.async.to.lds.b64' .. py:method:: globalPtr() -> _ods_ir .. py:method:: ldsPtr() -> _ods_ir .. py:method:: offset() -> _ods_ir .. py:method:: aux() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:function:: global_load_async_to_lds_b64(global_ptr: _ods_ir, lds_ptr: _ods_ir, offset: Union[int, _ods_ir], *, aux: Optional[Union[Any, _ods_ir]] = None, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> GlobalLoadAsyncToLDSB64Op .. py:class:: GlobalLoadAsyncToLDSB128Op(globalPtr: _ods_ir, ldsPtr: _ods_ir, offset: Union[int, _ods_ir], *, aux: Optional[Union[Any, _ods_ir]] = None, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Asynchronously loads 128 bits of data from a global memory pointer to a Local Data Share (LDS) pointer. Available on gfx1250+. Example: .. code:: mlir // Async 128-bit load from global to LDS. rocdl.global.load.async.to.lds.b128 %src, %dst, 0, 0 : !llvm.ptr<1>, !llvm.ptr<3> .. py:attribute:: OPERATION_NAME :value: 'rocdl.global.load.async.to.lds.b128' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: globalPtr() -> _ods_ir .. py:method:: ldsPtr() -> _ods_ir .. py:method:: offset() -> _ods_ir .. py:method:: aux() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:class:: GlobalLoadAsyncToLDSB128OpAdaptor(operands: list[Value], attributes: OpAttributeMap) GlobalLoadAsyncToLDSB128OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.global.load.async.to.lds.b128' .. py:method:: globalPtr() -> _ods_ir .. py:method:: ldsPtr() -> _ods_ir .. py:method:: offset() -> _ods_ir .. py:method:: aux() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:function:: global_load_async_to_lds_b128(global_ptr: _ods_ir, lds_ptr: _ods_ir, offset: Union[int, _ods_ir], *, aux: Optional[Union[Any, _ods_ir]] = None, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> GlobalLoadAsyncToLDSB128Op .. py:class:: GlobalLoadLDSOp(globalPtr: _ods_ir, ldsPtr: _ods_ir, size: Union[int, _ods_ir], offset: Union[int, _ods_ir], *, aux: Optional[Union[Any, _ods_ir]] = None, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.global.load.lds' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: globalPtr() -> _ods_ir .. py:method:: ldsPtr() -> _ods_ir .. py:method:: size() -> _ods_ir .. py:method:: offset() -> _ods_ir .. py:method:: aux() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:class:: GlobalLoadLDSOpAdaptor(operands: list[Value], attributes: OpAttributeMap) GlobalLoadLDSOpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.global.load.lds' .. py:method:: globalPtr() -> _ods_ir .. py:method:: ldsPtr() -> _ods_ir .. py:method:: size() -> _ods_ir .. py:method:: offset() -> _ods_ir .. py:method:: aux() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:function:: global_load_lds(global_ptr: _ods_ir, lds_ptr: _ods_ir, size: Union[int, _ods_ir], offset: Union[int, _ods_ir], *, aux: Optional[Union[Any, _ods_ir]] = None, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> GlobalLoadLDSOp .. py:class:: GlobalLoadTr4_B64(res: _ods_ir, ptr: _ods_ir, *, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Load a matrix of 4-bit data from the global memory, transpose data between row-major and column-major order, and store the result into a 64-bit vector register. Available in gfx1250+. Example (concrete mnemonics depend on address space and element size): .. code:: mlir // 64-bit transpose load from global memory. %0 = rocdl.global.load.tr4.b64 %ptr : !llvm.ptr<1> -> vector<2xi32> // 128-bit transpose load from global memory with f16 result. %1 = rocdl.global.load.tr.b128 %ptr : !llvm.ptr<1> -> vector<8xf16> // 64-bit transpose load from LDS. %2 = rocdl.ds.load.tr4.b64 %ptr : !llvm.ptr<3> -> vector<2xi32> // 128-bit transpose load from LDS with bf16 result. %3 = rocdl.ds.load.tr16.b128 %ptr : !llvm.ptr<3> -> vector<8xbf16> .. py:attribute:: OPERATION_NAME :value: 'rocdl.global.load.tr4.b64' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: ptr() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:method:: res() -> _ods_ir .. py:class:: GlobalLoadTr4_B64Adaptor(operands: list[Value], attributes: OpAttributeMap) GlobalLoadTr4_B64Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.global.load.tr4.b64' .. py:method:: ptr() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:function:: global_load_tr4_b64(res: _ods_ir, ptr: _ods_ir, *, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: GlobalLoadTr6_B96(res: _ods_ir, ptr: _ods_ir, *, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Load a matrix of 6-bit data from the global memory, transpose data between row-major and column-major order, and store the result into a 96-bit vector register. Available in gfx1250+. Example (concrete mnemonics depend on address space and element size): .. code:: mlir // 64-bit transpose load from global memory. %0 = rocdl.global.load.tr4.b64 %ptr : !llvm.ptr<1> -> vector<2xi32> // 128-bit transpose load from global memory with f16 result. %1 = rocdl.global.load.tr.b128 %ptr : !llvm.ptr<1> -> vector<8xf16> // 64-bit transpose load from LDS. %2 = rocdl.ds.load.tr4.b64 %ptr : !llvm.ptr<3> -> vector<2xi32> // 128-bit transpose load from LDS with bf16 result. %3 = rocdl.ds.load.tr16.b128 %ptr : !llvm.ptr<3> -> vector<8xbf16> .. py:attribute:: OPERATION_NAME :value: 'rocdl.global.load.tr6.b96' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: ptr() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:method:: res() -> _ods_ir .. py:class:: GlobalLoadTr6_B96Adaptor(operands: list[Value], attributes: OpAttributeMap) GlobalLoadTr6_B96Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.global.load.tr6.b96' .. py:method:: ptr() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:function:: global_load_tr6_b96(res: _ods_ir, ptr: _ods_ir, *, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: GlobalLoadTr8_B64(res: _ods_ir, ptr: _ods_ir, *, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Load a matrix of 8-bit data from the global memory, transpose data between row-major and column-major order, and store the result into a 64-bit vector register. Available in gfx1250+. Example (concrete mnemonics depend on address space and element size): .. code:: mlir // 64-bit transpose load from global memory. %0 = rocdl.global.load.tr4.b64 %ptr : !llvm.ptr<1> -> vector<2xi32> // 128-bit transpose load from global memory with f16 result. %1 = rocdl.global.load.tr.b128 %ptr : !llvm.ptr<1> -> vector<8xf16> // 64-bit transpose load from LDS. %2 = rocdl.ds.load.tr4.b64 %ptr : !llvm.ptr<3> -> vector<2xi32> // 128-bit transpose load from LDS with bf16 result. %3 = rocdl.ds.load.tr16.b128 %ptr : !llvm.ptr<3> -> vector<8xbf16> .. py:attribute:: OPERATION_NAME :value: 'rocdl.global.load.tr.b64' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: ptr() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:method:: res() -> _ods_ir .. py:class:: GlobalLoadTr8_B64Adaptor(operands: list[Value], attributes: OpAttributeMap) GlobalLoadTr8_B64Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.global.load.tr.b64' .. py:method:: ptr() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:function:: global_load_tr_b64(res: _ods_ir, ptr: _ods_ir, *, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: GlobalLoadTr8_B128(res: _ods_ir, ptr: _ods_ir, *, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Load a matrix of 16-bit data from the global memory, transpose data between row-major and column-major order, and store the result into a 128-bit vector register. Available in gfx1250+. Example (concrete mnemonics depend on address space and element size): .. code:: mlir // 64-bit transpose load from global memory. %0 = rocdl.global.load.tr4.b64 %ptr : !llvm.ptr<1> -> vector<2xi32> // 128-bit transpose load from global memory with f16 result. %1 = rocdl.global.load.tr.b128 %ptr : !llvm.ptr<1> -> vector<8xf16> // 64-bit transpose load from LDS. %2 = rocdl.ds.load.tr4.b64 %ptr : !llvm.ptr<3> -> vector<2xi32> // 128-bit transpose load from LDS with bf16 result. %3 = rocdl.ds.load.tr16.b128 %ptr : !llvm.ptr<3> -> vector<8xbf16> .. py:attribute:: OPERATION_NAME :value: 'rocdl.global.load.tr.b128' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: ptr() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:method:: res() -> _ods_ir .. py:class:: GlobalLoadTr8_B128Adaptor(operands: list[Value], attributes: OpAttributeMap) GlobalLoadTr8_B128Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.global.load.tr.b128' .. py:method:: ptr() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:function:: global_load_tr_b128(res: _ods_ir, ptr: _ods_ir, *, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: GlobalPrefetchOp(ptr: _ods_ir, *, cachePolicy: Optional[Union[Any, _ods_ir]] = None, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Prefetches 1 byte of data per lane from global memory into the WGP-cache or L2-cache. Available on gfx1250+. Example: .. code:: mlir // Prefetch from global memory into cache. rocdl.global.prefetch %ptr, 0 : !llvm.ptr<1> .. py:attribute:: OPERATION_NAME :value: 'rocdl.global.prefetch' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: ptr() -> _ods_ir .. py:method:: cachePolicy() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:class:: GlobalPrefetchOpAdaptor(operands: list[Value], attributes: OpAttributeMap) GlobalPrefetchOpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.global.prefetch' .. py:method:: ptr() -> _ods_ir .. py:method:: cachePolicy() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:function:: global_prefetch(ptr: _ods_ir, *, cache_policy: Optional[Union[Any, _ods_ir]] = None, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> GlobalPrefetchOp .. py:class:: GlobalStoreAsyncFromLDSB8Op(globalPtr: _ods_ir, ldsPtr: _ods_ir, offset: Union[int, _ods_ir], *, aux: Optional[Union[Any, _ods_ir]] = None, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Asynchronously stores 8 bits of data from a Local Data Share (LDS) pointer to a global memory pointer. Available on gfx1250+. Example: .. code:: mlir // Async 8-bit store from LDS to global. rocdl.global.store.async.from.lds.b8 %dst, %src, 0, 0 : !llvm.ptr<1>, !llvm.ptr<3> .. py:attribute:: OPERATION_NAME :value: 'rocdl.global.store.async.from.lds.b8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: globalPtr() -> _ods_ir .. py:method:: ldsPtr() -> _ods_ir .. py:method:: offset() -> _ods_ir .. py:method:: aux() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:class:: GlobalStoreAsyncFromLDSB8OpAdaptor(operands: list[Value], attributes: OpAttributeMap) GlobalStoreAsyncFromLDSB8OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.global.store.async.from.lds.b8' .. py:method:: globalPtr() -> _ods_ir .. py:method:: ldsPtr() -> _ods_ir .. py:method:: offset() -> _ods_ir .. py:method:: aux() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:function:: global_store_async_from_lds_b8(global_ptr: _ods_ir, lds_ptr: _ods_ir, offset: Union[int, _ods_ir], *, aux: Optional[Union[Any, _ods_ir]] = None, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> GlobalStoreAsyncFromLDSB8Op .. py:class:: GlobalStoreAsyncFromLDSB32Op(globalPtr: _ods_ir, ldsPtr: _ods_ir, offset: Union[int, _ods_ir], *, aux: Optional[Union[Any, _ods_ir]] = None, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Asynchronously stores 32 bits of data from a Local Data Share (LDS) pointer to a global memory pointer. Available on gfx1250+. Example: .. code:: mlir // Async 32-bit store from LDS to global. rocdl.global.store.async.from.lds.b32 %dst, %src, 0, 0 : !llvm.ptr<1>, !llvm.ptr<3> .. py:attribute:: OPERATION_NAME :value: 'rocdl.global.store.async.from.lds.b32' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: globalPtr() -> _ods_ir .. py:method:: ldsPtr() -> _ods_ir .. py:method:: offset() -> _ods_ir .. py:method:: aux() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:class:: GlobalStoreAsyncFromLDSB32OpAdaptor(operands: list[Value], attributes: OpAttributeMap) GlobalStoreAsyncFromLDSB32OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.global.store.async.from.lds.b32' .. py:method:: globalPtr() -> _ods_ir .. py:method:: ldsPtr() -> _ods_ir .. py:method:: offset() -> _ods_ir .. py:method:: aux() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:function:: global_store_async_from_lds_b32(global_ptr: _ods_ir, lds_ptr: _ods_ir, offset: Union[int, _ods_ir], *, aux: Optional[Union[Any, _ods_ir]] = None, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> GlobalStoreAsyncFromLDSB32Op .. py:class:: GlobalStoreAsyncFromLDSB64Op(globalPtr: _ods_ir, ldsPtr: _ods_ir, offset: Union[int, _ods_ir], *, aux: Optional[Union[Any, _ods_ir]] = None, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Asynchronously stores 64 bits of data from a Local Data Share (LDS) pointer to a global memory pointer. Available on gfx1250+. Example: .. code:: mlir // Async 64-bit store from LDS to global. rocdl.global.store.async.from.lds.b64 %dst, %src, 0, 0 : !llvm.ptr<1>, !llvm.ptr<3> .. py:attribute:: OPERATION_NAME :value: 'rocdl.global.store.async.from.lds.b64' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: globalPtr() -> _ods_ir .. py:method:: ldsPtr() -> _ods_ir .. py:method:: offset() -> _ods_ir .. py:method:: aux() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:class:: GlobalStoreAsyncFromLDSB64OpAdaptor(operands: list[Value], attributes: OpAttributeMap) GlobalStoreAsyncFromLDSB64OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.global.store.async.from.lds.b64' .. py:method:: globalPtr() -> _ods_ir .. py:method:: ldsPtr() -> _ods_ir .. py:method:: offset() -> _ods_ir .. py:method:: aux() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:function:: global_store_async_from_lds_b64(global_ptr: _ods_ir, lds_ptr: _ods_ir, offset: Union[int, _ods_ir], *, aux: Optional[Union[Any, _ods_ir]] = None, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> GlobalStoreAsyncFromLDSB64Op .. py:class:: GlobalStoreAsyncFromLDSB128Op(globalPtr: _ods_ir, ldsPtr: _ods_ir, offset: Union[int, _ods_ir], *, aux: Optional[Union[Any, _ods_ir]] = None, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Asynchronously stores 128 bits of data from a Local Data Share (LDS) pointer to a global memory pointer. Available on gfx1250+. Example: .. code:: mlir // Async 128-bit store from LDS to global. rocdl.global.store.async.from.lds.b128 %dst, %src, 0, 0 : !llvm.ptr<1>, !llvm.ptr<3> .. py:attribute:: OPERATION_NAME :value: 'rocdl.global.store.async.from.lds.b128' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: globalPtr() -> _ods_ir .. py:method:: ldsPtr() -> _ods_ir .. py:method:: offset() -> _ods_ir .. py:method:: aux() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:class:: GlobalStoreAsyncFromLDSB128OpAdaptor(operands: list[Value], attributes: OpAttributeMap) GlobalStoreAsyncFromLDSB128OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.global.store.async.from.lds.b128' .. py:method:: globalPtr() -> _ods_ir .. py:method:: ldsPtr() -> _ods_ir .. py:method:: offset() -> _ods_ir .. py:method:: aux() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:function:: global_store_async_from_lds_b128(global_ptr: _ods_ir, lds_ptr: _ods_ir, offset: Union[int, _ods_ir], *, aux: Optional[Union[Any, _ods_ir]] = None, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> GlobalStoreAsyncFromLDSB128Op .. py:class:: IglpOpt(variant: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Instruction-group-level parallelism optimization hint. Example: .. code:: mlir // IGLP optimization hint variant 0. rocdl.iglp.opt 0 .. py:attribute:: OPERATION_NAME :value: 'rocdl.iglp.opt' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: variant() -> _ods_ir .. py:class:: IglpOptAdaptor(operands: list[Value], attributes: OpAttributeMap) IglpOptAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.iglp.opt' .. py:method:: variant() -> _ods_ir .. py:function:: iglp_opt(variant: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> IglpOpt .. py:class:: LoadAsyncToLDSOp(globalPtr: _ods_ir, ldsPtr: _ods_ir, size: Union[int, _ods_ir], offset: Union[int, _ods_ir], *, aux: Optional[Union[Any, _ods_ir]] = None, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Load ``size`` bytes (the valid sizes vary by architecture) from the global memory pointed to by ``globalPtr`` and put them at ``ldsPtr``, concantenating (and applying padding for sizes less than 4 bytes, along with padding out 12-byte reads to 16-byte writes). The value of ``globalPtr`` can vary between lanes, while ``sharedPtr`` must be subgroup-uniform (the values from each lane are concatentated before being written to LDS with appropriate padding applied.) ``offset`` is a constant offset applied to **both** pointers, and ``aux`` sets the cache policy. Unlike ``rocdl.load.to.lds``, the compiler will not automatically inserts waits for this load to complete at the point it thinks you're using a region of LDS you've stored values to - you need to use the ``rocdl.asyncmark`` and ``rocdl.wait.asyncmark`` operations to explicitly group these operations and wait for their completion. Available on gfx10 and earlier with varying suppported values of ``size``. Example: .. code:: mlir // Async load 4 bytes from global pointer to LDS. rocdl.load.async.to.lds %global, %shared, 4, 0, 0 : !llvm.ptr<1>, !llvm.ptr<3> // Async load 4 bytes from fat buffer pointer to LDS. rocdl.load.async.to.lds %fatBuffer, %shared, 4, 0, 0 : !llvm.ptr<7>, !llvm.ptr<3> .. py:attribute:: OPERATION_NAME :value: 'rocdl.load.async.to.lds' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: globalPtr() -> _ods_ir .. py:method:: ldsPtr() -> _ods_ir .. py:method:: size() -> _ods_ir .. py:method:: offset() -> _ods_ir .. py:method:: aux() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:class:: LoadAsyncToLDSOpAdaptor(operands: list[Value], attributes: OpAttributeMap) LoadAsyncToLDSOpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.load.async.to.lds' .. py:method:: globalPtr() -> _ods_ir .. py:method:: ldsPtr() -> _ods_ir .. py:method:: size() -> _ods_ir .. py:method:: offset() -> _ods_ir .. py:method:: aux() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:function:: load_async_to_lds(global_ptr: _ods_ir, lds_ptr: _ods_ir, size: Union[int, _ods_ir], offset: Union[int, _ods_ir], *, aux: Optional[Union[Any, _ods_ir]] = None, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> LoadAsyncToLDSOp .. py:class:: LoadToLDSOp(globalPtr: _ods_ir, ldsPtr: _ods_ir, size: Union[int, _ods_ir], offset: Union[int, _ods_ir], *, aux: Optional[Union[Any, _ods_ir]] = None, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.load.to.lds' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: globalPtr() -> _ods_ir .. py:method:: ldsPtr() -> _ods_ir .. py:method:: size() -> _ods_ir .. py:method:: offset() -> _ods_ir .. py:method:: aux() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:class:: LoadToLDSOpAdaptor(operands: list[Value], attributes: OpAttributeMap) LoadToLDSOpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.load.to.lds' .. py:method:: globalPtr() -> _ods_ir .. py:method:: ldsPtr() -> _ods_ir .. py:method:: size() -> _ods_ir .. py:method:: offset() -> _ods_ir .. py:method:: aux() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:function:: load_to_lds(global_ptr: _ods_ir, lds_ptr: _ods_ir, size: Union[int, _ods_ir], offset: Union[int, _ods_ir], *, aux: Optional[Union[Any, _ods_ir]] = None, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> LoadToLDSOp .. py:class:: MakeBufferRsrcOp(res: _ods_ir, base: _ods_ir, stride: _ods_ir[_ods_ir], numRecords: _ods_ir[_ods_ir], flags: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.make.buffer.rsrc' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: base() -> _ods_ir .. py:method:: stride() -> _ods_ir[_ods_ir] .. py:method:: numRecords() -> _ods_ir[_ods_ir] .. py:method:: flags() -> _ods_ir[_ods_ir] .. py:method:: res() -> _ods_ir .. py:class:: MakeBufferRsrcOpAdaptor(operands: list[Value], attributes: OpAttributeMap) MakeBufferRsrcOpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.make.buffer.rsrc' .. py:method:: base() -> _ods_ir .. py:method:: stride() -> _ods_ir[_ods_ir] .. py:method:: numRecords() -> _ods_ir[_ods_ir] .. py:method:: flags() -> _ods_ir[_ods_ir] .. py:function:: make_buffer_rsrc(res: _ods_ir, base: _ods_ir, stride: _ods_ir[_ods_ir], num_records: _ods_ir[_ods_ir], flags: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: MbcntHiOp(res: _ods_ir, in0: _ods_ir[_ods_ir], in1: _ods_ir[_ods_ir], *, arg_attrs: Optional[Union[Any, _ods_ir]] = None, res_attrs: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Masked bit count of threads below the current lane in a wavefront. ``in0`` is a 32-bit mask that is AND-ed with the relevant half of the execution mask and the bits below the current lane; ``in1`` is added to the resulting popcount: * **lo**: ``in1 + popcount(in0 & exec_lo & ((1 << min(lane_id, 32)) - 1))`` * **hi**: ``in1 + popcount(in0 & exec_hi & ((1 << saturating_usub(lane_id, 32)) - 1))`` To obtain a unique thread index within a wave64, chain the two ops with ``in0 = -1`` (all bits set): Example: .. code:: mlir %all_ones = arith.constant -1 : i32 %zero = arith.constant 0 : i32 // Count active threads below this lane in the low 32 lanes. %lo = rocdl.mbcnt.lo %all_ones, %zero : (i32, i32) -> i32 // Add the count from the high 32 lanes to get the full lane index. %hi = rocdl.mbcnt.hi %all_ones, %lo : (i32, i32) -> i32 .. py:attribute:: OPERATION_NAME :value: 'rocdl.mbcnt.hi' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: in0() -> _ods_ir[_ods_ir] .. py:method:: in1() -> _ods_ir[_ods_ir] .. py:method:: arg_attrs() -> Optional[_ods_ir] .. py:method:: res_attrs() -> Optional[_ods_ir] .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: MbcntHiOpAdaptor(operands: list[Value], attributes: OpAttributeMap) MbcntHiOpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.mbcnt.hi' .. py:method:: in0() -> _ods_ir[_ods_ir] .. py:method:: in1() -> _ods_ir[_ods_ir] .. py:method:: arg_attrs() -> Optional[_ods_ir] .. py:method:: res_attrs() -> Optional[_ods_ir] .. py:function:: mbcnt_hi(res: _ods_ir, in0: _ods_ir[_ods_ir], in1: _ods_ir[_ods_ir], *, arg_attrs: Optional[Union[Any, _ods_ir]] = None, res_attrs: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: MbcntLoOp(res: _ods_ir, in0: _ods_ir[_ods_ir], in1: _ods_ir[_ods_ir], *, arg_attrs: Optional[Union[Any, _ods_ir]] = None, res_attrs: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Masked bit count of threads below the current lane in a wavefront. ``in0`` is a 32-bit mask that is AND-ed with the relevant half of the execution mask and the bits below the current lane; ``in1`` is added to the resulting popcount: * **lo**: ``in1 + popcount(in0 & exec_lo & ((1 << min(lane_id, 32)) - 1))`` * **hi**: ``in1 + popcount(in0 & exec_hi & ((1 << saturating_usub(lane_id, 32)) - 1))`` To obtain a unique thread index within a wave64, chain the two ops with ``in0 = -1`` (all bits set): Example: .. code:: mlir %all_ones = arith.constant -1 : i32 %zero = arith.constant 0 : i32 // Count active threads below this lane in the low 32 lanes. %lo = rocdl.mbcnt.lo %all_ones, %zero : (i32, i32) -> i32 // Add the count from the high 32 lanes to get the full lane index. %hi = rocdl.mbcnt.hi %all_ones, %lo : (i32, i32) -> i32 .. py:attribute:: OPERATION_NAME :value: 'rocdl.mbcnt.lo' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: in0() -> _ods_ir[_ods_ir] .. py:method:: in1() -> _ods_ir[_ods_ir] .. py:method:: arg_attrs() -> Optional[_ods_ir] .. py:method:: res_attrs() -> Optional[_ods_ir] .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: MbcntLoOpAdaptor(operands: list[Value], attributes: OpAttributeMap) MbcntLoOpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.mbcnt.lo' .. py:method:: in0() -> _ods_ir[_ods_ir] .. py:method:: in1() -> _ods_ir[_ods_ir] .. py:method:: arg_attrs() -> Optional[_ods_ir] .. py:method:: res_attrs() -> Optional[_ods_ir] .. py:function:: mbcnt_lo(res: _ods_ir, in0: _ods_ir[_ods_ir], in1: _ods_ir[_ods_ir], *, arg_attrs: Optional[Union[Any, _ods_ir]] = None, res_attrs: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: Permlane16SwapOp(res: _ods_ir, old: _ods_ir[_ods_ir], src: _ods_ir[_ods_ir], fi: Union[bool, _ods_ir], boundControl: Union[bool, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Performs a ``permlane16.swap`` operation with the given operands, applying the permutation specified by $fi to the provided inputs. Example: .. code:: mlir // Swap lanes between groups of 16 threads. %res = rocdl.permlane16.swap %src, %src, 0, -1 : (i32, i32) -> !llvm.struct<(i32, i32)> .. py:attribute:: OPERATION_NAME :value: 'rocdl.permlane16.swap' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: old() -> _ods_ir[_ods_ir] .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: fi() -> _ods_ir .. py:method:: boundControl() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: Permlane16SwapOpAdaptor(operands: list[Value], attributes: OpAttributeMap) Permlane16SwapOpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.permlane16.swap' .. py:method:: old() -> _ods_ir[_ods_ir] .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: fi() -> _ods_ir .. py:method:: boundControl() -> _ods_ir .. py:function:: permlane16_swap(res: _ods_ir, old: _ods_ir[_ods_ir], src: _ods_ir[_ods_ir], fi: Union[bool, _ods_ir], bound_control: Union[bool, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: Permlane16VarOp(res: _ods_ir, old: _ods_ir[_ods_ir], src0: _ods_ir[_ods_ir], src1: _ods_ir[_ods_ir], fi: Union[bool, _ods_ir], boundControl: Union[bool, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Performs a ``permlane16.var`` operation: a per-lane variable-selector intra-row permutation (within each 16-lane row). Maps to ``llvm.amdgcn.permlane16.var``. Each destination lane within a 16-lane row reads its value from the source lane whose index is given by the corresponding per-lane entry in ``$src1`` (a VGPR). ``$fi`` and ``$boundControl`` are immediate i1 attrs matching the underlying intrinsic's modifiers. Example: .. code:: mlir %res = rocdl.permlane16.var %old, %src, %selector, false, true : (i32, i32, i32) -> i32 .. py:attribute:: OPERATION_NAME :value: 'rocdl.permlane16.var' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: old() -> _ods_ir[_ods_ir] .. py:method:: src0() -> _ods_ir[_ods_ir] .. py:method:: src1() -> _ods_ir[_ods_ir] .. py:method:: fi() -> _ods_ir .. py:method:: boundControl() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: Permlane16VarOpAdaptor(operands: list[Value], attributes: OpAttributeMap) Permlane16VarOpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.permlane16.var' .. py:method:: old() -> _ods_ir[_ods_ir] .. py:method:: src0() -> _ods_ir[_ods_ir] .. py:method:: src1() -> _ods_ir[_ods_ir] .. py:method:: fi() -> _ods_ir .. py:method:: boundControl() -> _ods_ir .. py:function:: permlane16_var(res: _ods_ir, old: _ods_ir[_ods_ir], src0: _ods_ir[_ods_ir], src1: _ods_ir[_ods_ir], fi: Union[bool, _ods_ir], bound_control: Union[bool, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: Permlane32SwapOp(res: _ods_ir, old: _ods_ir[_ods_ir], src: _ods_ir[_ods_ir], fi: Union[bool, _ods_ir], boundControl: Union[bool, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Performs a ``permlane32.swap`` operation with the given operands, applying the permutation specified by $fi to the provided inputs. Example: .. code:: mlir // Swap lanes between groups of 32 threads. %res = rocdl.permlane32.swap %src, %src, 0, -1 : (i32, i32) -> !llvm.struct<(i32, i32)> .. py:attribute:: OPERATION_NAME :value: 'rocdl.permlane32.swap' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: old() -> _ods_ir[_ods_ir] .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: fi() -> _ods_ir .. py:method:: boundControl() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: Permlane32SwapOpAdaptor(operands: list[Value], attributes: OpAttributeMap) Permlane32SwapOpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.permlane32.swap' .. py:method:: old() -> _ods_ir[_ods_ir] .. py:method:: src() -> _ods_ir[_ods_ir] .. py:method:: fi() -> _ods_ir .. py:method:: boundControl() -> _ods_ir .. py:function:: permlane32_swap(res: _ods_ir, old: _ods_ir[_ods_ir], src: _ods_ir[_ods_ir], fi: Union[bool, _ods_ir], bound_control: Union[bool, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: PermlaneX16Op(res: _ods_ir, old: _ods_ir, src0: _ods_ir, src1: _ods_ir, src2: _ods_ir, fi: Union[bool, _ods_ir], boundControl: Union[bool, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Performs a ``permlanex16`` operation with the given operands, applying the permutation specified by $fi to the provided inputs. Example: .. code:: mlir // Scalar permlanex16. %ret0 = rocdl.permlanex16 %src0, %src0, %sel, %sel, 0, -1 : f32, i32 // Vector permlanex16. %ret1 = rocdl.permlanex16 %src1, %src1, %sel, %sel, 0, -1 : vector<2xf32>, i32 .. py:attribute:: OPERATION_NAME :value: 'rocdl.permlanex16' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: old() -> _ods_ir .. py:method:: src0() -> _ods_ir .. py:method:: src1() -> _ods_ir .. py:method:: src2() -> _ods_ir .. py:method:: fi() -> _ods_ir .. py:method:: boundControl() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: PermlaneX16OpAdaptor(operands: list[Value], attributes: OpAttributeMap) PermlaneX16OpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.permlanex16' .. py:method:: old() -> _ods_ir .. py:method:: src0() -> _ods_ir .. py:method:: src1() -> _ods_ir .. py:method:: src2() -> _ods_ir .. py:method:: fi() -> _ods_ir .. py:method:: boundControl() -> _ods_ir .. py:function:: permlanex16(res: _ods_ir, old: _ods_ir, src0: _ods_ir, src1: _ods_ir, src2: _ods_ir, fi: Union[bool, _ods_ir], bound_control: Union[bool, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: PermlaneX16VarOp(res: _ods_ir, old: _ods_ir[_ods_ir], src0: _ods_ir[_ods_ir], src1: _ods_ir[_ods_ir], fi: Union[bool, _ods_ir], boundControl: Union[bool, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Performs a ``permlanex16.var`` operation: a per-lane variable-selector cross-row permutation (each lane in one 16-lane row reads from a per-lane-chosen source lane in the opposite row). Maps to ``llvm.amdgcn.permlanex16.var``. With per-lane "identity" selectors this realises an XOR-16 swap pattern in pure VALU; with arbitrary selectors it enables general per-lane cross-half-wave permutations. ``$fi`` and ``$boundControl`` are immediate i1 attrs matching the underlying intrinsic's modifiers. Example: .. code:: mlir %res = rocdl.permlanex16.var %old, %src, %selector, false, true : (i32, i32, i32) -> i32 .. py:attribute:: OPERATION_NAME :value: 'rocdl.permlanex16.var' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: old() -> _ods_ir[_ods_ir] .. py:method:: src0() -> _ods_ir[_ods_ir] .. py:method:: src1() -> _ods_ir[_ods_ir] .. py:method:: fi() -> _ods_ir .. py:method:: boundControl() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: PermlaneX16VarOpAdaptor(operands: list[Value], attributes: OpAttributeMap) PermlaneX16VarOpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.permlanex16.var' .. py:method:: old() -> _ods_ir[_ods_ir] .. py:method:: src0() -> _ods_ir[_ods_ir] .. py:method:: src1() -> _ods_ir[_ods_ir] .. py:method:: fi() -> _ods_ir .. py:method:: boundControl() -> _ods_ir .. py:function:: permlanex16_var(res: _ods_ir, old: _ods_ir[_ods_ir], src0: _ods_ir[_ods_ir], src1: _ods_ir[_ods_ir], fi: Union[bool, _ods_ir], bound_control: Union[bool, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: PtrSBufferLoadOp(res: _ods_ir, rsrc: _ods_ir, offset: _ods_ir[_ods_ir], *, aux: Optional[Union[Any, _ods_ir]] = None, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.ptr.s.buffer.load' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: rsrc() -> _ods_ir .. py:method:: offset() -> _ods_ir[_ods_ir] .. py:method:: aux() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:method:: res() -> _ods_ir .. py:class:: PtrSBufferLoadOpAdaptor(operands: list[Value], attributes: OpAttributeMap) PtrSBufferLoadOpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.ptr.s.buffer.load' .. py:method:: rsrc() -> _ods_ir .. py:method:: offset() -> _ods_ir[_ods_ir] .. py:method:: aux() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:function:: ptr_s_buffer_load(res: _ods_ir, rsrc: _ods_ir, offset: _ods_ir[_ods_ir], *, aux: Optional[Union[Any, _ods_ir]] = None, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: RawBufferAtomicCmpSwap(res: _ods_ir, src: _ods_ir, cmp: _ods_ir, rsrc: _ods_ir[_ods_ir], offset: _ods_ir[_ods_ir], soffset: _ods_ir[_ods_ir], *, aux: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.raw.buffer.atomic.cmpswap' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: src() -> _ods_ir .. py:method:: cmp() -> _ods_ir .. py:method:: rsrc() -> _ods_ir[_ods_ir] .. py:method:: offset() -> _ods_ir[_ods_ir] .. py:method:: soffset() -> _ods_ir[_ods_ir] .. py:method:: aux() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: RawBufferAtomicCmpSwapAdaptor(operands: list[Value], attributes: OpAttributeMap) RawBufferAtomicCmpSwapAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.raw.buffer.atomic.cmpswap' .. py:method:: src() -> _ods_ir .. py:method:: cmp() -> _ods_ir .. py:method:: rsrc() -> _ods_ir[_ods_ir] .. py:method:: offset() -> _ods_ir[_ods_ir] .. py:method:: soffset() -> _ods_ir[_ods_ir] .. py:method:: aux() -> _ods_ir .. py:function:: raw_buffer_atomic_cmpswap(res: _ods_ir, src: _ods_ir, cmp: _ods_ir, rsrc: _ods_ir[_ods_ir], offset: _ods_ir[_ods_ir], soffset: _ods_ir[_ods_ir], *, aux: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: RawBufferAtomicFAddOp(res: _ods_ir, vdata: _ods_ir, rsrc: _ods_ir[_ods_ir], offset: _ods_ir[_ods_ir], soffset: _ods_ir[_ods_ir], *, aux: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.raw.buffer.atomic.fadd' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: vdata() -> _ods_ir .. py:method:: rsrc() -> _ods_ir[_ods_ir] .. py:method:: offset() -> _ods_ir[_ods_ir] .. py:method:: soffset() -> _ods_ir[_ods_ir] .. py:method:: aux() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: RawBufferAtomicFAddOpAdaptor(operands: list[Value], attributes: OpAttributeMap) RawBufferAtomicFAddOpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.raw.buffer.atomic.fadd' .. py:method:: vdata() -> _ods_ir .. py:method:: rsrc() -> _ods_ir[_ods_ir] .. py:method:: offset() -> _ods_ir[_ods_ir] .. py:method:: soffset() -> _ods_ir[_ods_ir] .. py:method:: aux() -> _ods_ir .. py:function:: raw_buffer_atomic_fadd(res: _ods_ir, vdata: _ods_ir, rsrc: _ods_ir[_ods_ir], offset: _ods_ir[_ods_ir], soffset: _ods_ir[_ods_ir], *, aux: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: RawBufferAtomicFMaxOp(res: _ods_ir, vdata: _ods_ir, rsrc: _ods_ir[_ods_ir], offset: _ods_ir[_ods_ir], soffset: _ods_ir[_ods_ir], *, aux: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.raw.buffer.atomic.fmax' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: vdata() -> _ods_ir .. py:method:: rsrc() -> _ods_ir[_ods_ir] .. py:method:: offset() -> _ods_ir[_ods_ir] .. py:method:: soffset() -> _ods_ir[_ods_ir] .. py:method:: aux() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: RawBufferAtomicFMaxOpAdaptor(operands: list[Value], attributes: OpAttributeMap) RawBufferAtomicFMaxOpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.raw.buffer.atomic.fmax' .. py:method:: vdata() -> _ods_ir .. py:method:: rsrc() -> _ods_ir[_ods_ir] .. py:method:: offset() -> _ods_ir[_ods_ir] .. py:method:: soffset() -> _ods_ir[_ods_ir] .. py:method:: aux() -> _ods_ir .. py:function:: raw_buffer_atomic_fmax(res: _ods_ir, vdata: _ods_ir, rsrc: _ods_ir[_ods_ir], offset: _ods_ir[_ods_ir], soffset: _ods_ir[_ods_ir], *, aux: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: RawBufferAtomicSMaxOp(res: _ods_ir, vdata: _ods_ir, rsrc: _ods_ir[_ods_ir], offset: _ods_ir[_ods_ir], soffset: _ods_ir[_ods_ir], *, aux: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.raw.buffer.atomic.smax' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: vdata() -> _ods_ir .. py:method:: rsrc() -> _ods_ir[_ods_ir] .. py:method:: offset() -> _ods_ir[_ods_ir] .. py:method:: soffset() -> _ods_ir[_ods_ir] .. py:method:: aux() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: RawBufferAtomicSMaxOpAdaptor(operands: list[Value], attributes: OpAttributeMap) RawBufferAtomicSMaxOpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.raw.buffer.atomic.smax' .. py:method:: vdata() -> _ods_ir .. py:method:: rsrc() -> _ods_ir[_ods_ir] .. py:method:: offset() -> _ods_ir[_ods_ir] .. py:method:: soffset() -> _ods_ir[_ods_ir] .. py:method:: aux() -> _ods_ir .. py:function:: raw_buffer_atomic_smax(res: _ods_ir, vdata: _ods_ir, rsrc: _ods_ir[_ods_ir], offset: _ods_ir[_ods_ir], soffset: _ods_ir[_ods_ir], *, aux: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: RawBufferAtomicUMinOp(res: _ods_ir, vdata: _ods_ir, rsrc: _ods_ir[_ods_ir], offset: _ods_ir[_ods_ir], soffset: _ods_ir[_ods_ir], *, aux: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.raw.buffer.atomic.umin' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: vdata() -> _ods_ir .. py:method:: rsrc() -> _ods_ir[_ods_ir] .. py:method:: offset() -> _ods_ir[_ods_ir] .. py:method:: soffset() -> _ods_ir[_ods_ir] .. py:method:: aux() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: RawBufferAtomicUMinOpAdaptor(operands: list[Value], attributes: OpAttributeMap) RawBufferAtomicUMinOpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.raw.buffer.atomic.umin' .. py:method:: vdata() -> _ods_ir .. py:method:: rsrc() -> _ods_ir[_ods_ir] .. py:method:: offset() -> _ods_ir[_ods_ir] .. py:method:: soffset() -> _ods_ir[_ods_ir] .. py:method:: aux() -> _ods_ir .. py:function:: raw_buffer_atomic_umin(res: _ods_ir, vdata: _ods_ir, rsrc: _ods_ir[_ods_ir], offset: _ods_ir[_ods_ir], soffset: _ods_ir[_ods_ir], *, aux: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: RawBufferLoadOp(res: _ods_ir, rsrc: _ods_ir[_ods_ir], offset: _ods_ir[_ods_ir], soffset: _ods_ir[_ods_ir], *, aux: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.raw.buffer.load' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: rsrc() -> _ods_ir[_ods_ir] .. py:method:: offset() -> _ods_ir[_ods_ir] .. py:method:: soffset() -> _ods_ir[_ods_ir] .. py:method:: aux() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: RawBufferLoadOpAdaptor(operands: list[Value], attributes: OpAttributeMap) RawBufferLoadOpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.raw.buffer.load' .. py:method:: rsrc() -> _ods_ir[_ods_ir] .. py:method:: offset() -> _ods_ir[_ods_ir] .. py:method:: soffset() -> _ods_ir[_ods_ir] .. py:method:: aux() -> _ods_ir .. py:function:: raw_buffer_load(res: _ods_ir, rsrc: _ods_ir[_ods_ir], offset: _ods_ir[_ods_ir], soffset: _ods_ir[_ods_ir], *, aux: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: RawBufferStoreOp(vdata: _ods_ir, rsrc: _ods_ir[_ods_ir], offset: _ods_ir[_ods_ir], soffset: _ods_ir[_ods_ir], *, aux: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.raw.buffer.store' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: vdata() -> _ods_ir .. py:method:: rsrc() -> _ods_ir[_ods_ir] .. py:method:: offset() -> _ods_ir[_ods_ir] .. py:method:: soffset() -> _ods_ir[_ods_ir] .. py:method:: aux() -> _ods_ir .. py:class:: RawBufferStoreOpAdaptor(operands: list[Value], attributes: OpAttributeMap) RawBufferStoreOpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.raw.buffer.store' .. py:method:: vdata() -> _ods_ir .. py:method:: rsrc() -> _ods_ir[_ods_ir] .. py:method:: offset() -> _ods_ir[_ods_ir] .. py:method:: soffset() -> _ods_ir[_ods_ir] .. py:method:: aux() -> _ods_ir .. py:function:: raw_buffer_store(vdata: _ods_ir, rsrc: _ods_ir[_ods_ir], offset: _ods_ir[_ods_ir], soffset: _ods_ir[_ods_ir], *, aux: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> RawBufferStoreOp .. py:class:: RawPtrBufferAtomicCmpSwap(res: _ods_ir, src: _ods_ir, cmp: _ods_ir, rsrc: _ods_ir, offset: _ods_ir[_ods_ir], soffset: _ods_ir[_ods_ir], *, aux: Optional[Union[Any, _ods_ir]] = None, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.raw.ptr.buffer.atomic.cmpswap' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: src() -> _ods_ir .. py:method:: cmp() -> _ods_ir .. py:method:: rsrc() -> _ods_ir .. py:method:: offset() -> _ods_ir[_ods_ir] .. py:method:: soffset() -> _ods_ir[_ods_ir] .. py:method:: aux() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:method:: res() -> _ods_ir .. py:class:: RawPtrBufferAtomicCmpSwapAdaptor(operands: list[Value], attributes: OpAttributeMap) RawPtrBufferAtomicCmpSwapAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.raw.ptr.buffer.atomic.cmpswap' .. py:method:: src() -> _ods_ir .. py:method:: cmp() -> _ods_ir .. py:method:: rsrc() -> _ods_ir .. py:method:: offset() -> _ods_ir[_ods_ir] .. py:method:: soffset() -> _ods_ir[_ods_ir] .. py:method:: aux() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:function:: raw_ptr_buffer_atomic_cmpswap(res: _ods_ir, src: _ods_ir, cmp: _ods_ir, rsrc: _ods_ir, offset: _ods_ir[_ods_ir], soffset: _ods_ir[_ods_ir], *, aux: Optional[Union[Any, _ods_ir]] = None, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: RawPtrBufferAtomicFaddOp(res: _ods_ir, vdata: _ods_ir, rsrc: _ods_ir, offset: _ods_ir[_ods_ir], soffset: _ods_ir[_ods_ir], *, aux: Optional[Union[Any, _ods_ir]] = None, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.raw.ptr.buffer.atomic.fadd' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: vdata() -> _ods_ir .. py:method:: rsrc() -> _ods_ir .. py:method:: offset() -> _ods_ir[_ods_ir] .. py:method:: soffset() -> _ods_ir[_ods_ir] .. py:method:: aux() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:method:: res() -> _ods_ir .. py:class:: RawPtrBufferAtomicFaddOpAdaptor(operands: list[Value], attributes: OpAttributeMap) RawPtrBufferAtomicFaddOpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.raw.ptr.buffer.atomic.fadd' .. py:method:: vdata() -> _ods_ir .. py:method:: rsrc() -> _ods_ir .. py:method:: offset() -> _ods_ir[_ods_ir] .. py:method:: soffset() -> _ods_ir[_ods_ir] .. py:method:: aux() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:function:: raw_ptr_buffer_atomic_fadd(res: _ods_ir, vdata: _ods_ir, rsrc: _ods_ir, offset: _ods_ir[_ods_ir], soffset: _ods_ir[_ods_ir], *, aux: Optional[Union[Any, _ods_ir]] = None, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: RawPtrBufferAtomicFmaxOp(res: _ods_ir, vdata: _ods_ir, rsrc: _ods_ir, offset: _ods_ir[_ods_ir], soffset: _ods_ir[_ods_ir], *, aux: Optional[Union[Any, _ods_ir]] = None, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.raw.ptr.buffer.atomic.fmax' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: vdata() -> _ods_ir .. py:method:: rsrc() -> _ods_ir .. py:method:: offset() -> _ods_ir[_ods_ir] .. py:method:: soffset() -> _ods_ir[_ods_ir] .. py:method:: aux() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:method:: res() -> _ods_ir .. py:class:: RawPtrBufferAtomicFmaxOpAdaptor(operands: list[Value], attributes: OpAttributeMap) RawPtrBufferAtomicFmaxOpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.raw.ptr.buffer.atomic.fmax' .. py:method:: vdata() -> _ods_ir .. py:method:: rsrc() -> _ods_ir .. py:method:: offset() -> _ods_ir[_ods_ir] .. py:method:: soffset() -> _ods_ir[_ods_ir] .. py:method:: aux() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:function:: raw_ptr_buffer_atomic_fmax(res: _ods_ir, vdata: _ods_ir, rsrc: _ods_ir, offset: _ods_ir[_ods_ir], soffset: _ods_ir[_ods_ir], *, aux: Optional[Union[Any, _ods_ir]] = None, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: RawPtrBufferAtomicSmaxOp(res: _ods_ir, vdata: _ods_ir, rsrc: _ods_ir, offset: _ods_ir[_ods_ir], soffset: _ods_ir[_ods_ir], *, aux: Optional[Union[Any, _ods_ir]] = None, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.raw.ptr.buffer.atomic.smax' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: vdata() -> _ods_ir .. py:method:: rsrc() -> _ods_ir .. py:method:: offset() -> _ods_ir[_ods_ir] .. py:method:: soffset() -> _ods_ir[_ods_ir] .. py:method:: aux() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:method:: res() -> _ods_ir .. py:class:: RawPtrBufferAtomicSmaxOpAdaptor(operands: list[Value], attributes: OpAttributeMap) RawPtrBufferAtomicSmaxOpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.raw.ptr.buffer.atomic.smax' .. py:method:: vdata() -> _ods_ir .. py:method:: rsrc() -> _ods_ir .. py:method:: offset() -> _ods_ir[_ods_ir] .. py:method:: soffset() -> _ods_ir[_ods_ir] .. py:method:: aux() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:function:: raw_ptr_buffer_atomic_smax(res: _ods_ir, vdata: _ods_ir, rsrc: _ods_ir, offset: _ods_ir[_ods_ir], soffset: _ods_ir[_ods_ir], *, aux: Optional[Union[Any, _ods_ir]] = None, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: RawPtrBufferAtomicUminOp(res: _ods_ir, vdata: _ods_ir, rsrc: _ods_ir, offset: _ods_ir[_ods_ir], soffset: _ods_ir[_ods_ir], *, aux: Optional[Union[Any, _ods_ir]] = None, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.raw.ptr.buffer.atomic.umin' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: vdata() -> _ods_ir .. py:method:: rsrc() -> _ods_ir .. py:method:: offset() -> _ods_ir[_ods_ir] .. py:method:: soffset() -> _ods_ir[_ods_ir] .. py:method:: aux() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:method:: res() -> _ods_ir .. py:class:: RawPtrBufferAtomicUminOpAdaptor(operands: list[Value], attributes: OpAttributeMap) RawPtrBufferAtomicUminOpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.raw.ptr.buffer.atomic.umin' .. py:method:: vdata() -> _ods_ir .. py:method:: rsrc() -> _ods_ir .. py:method:: offset() -> _ods_ir[_ods_ir] .. py:method:: soffset() -> _ods_ir[_ods_ir] .. py:method:: aux() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:function:: raw_ptr_buffer_atomic_umin(res: _ods_ir, vdata: _ods_ir, rsrc: _ods_ir, offset: _ods_ir[_ods_ir], soffset: _ods_ir[_ods_ir], *, aux: Optional[Union[Any, _ods_ir]] = None, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: RawPtrBufferLoadAsyncLdsOp(rsrc: _ods_ir, ldsPtr: _ods_ir, size: _ods_ir[_ods_ir], voffset: _ods_ir[_ods_ir], soffset: _ods_ir[_ods_ir], offset: _ods_ir[_ods_ir], *, aux: Optional[Union[Any, _ods_ir]] = None, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Load from a buffer resource ``rsrc`` to ``ldsPtr``, which must be uniform. See ``rocdl.load.async.to.lds`` for overall semantics of such loads, noting that here ``voffset`` can be lane-varying and that ``rsrc`` (which holds the base addres) must, as always, be uniform. Available on gfx9 and gfx10. Example: .. code:: mlir // Async buffer load to LDS via buffer resource pointer. rocdl.raw.ptr.buffer.load.async.lds %rsrc, %ldsPtr, %size, %voffset, %soffset, %offset, 0 .. py:attribute:: OPERATION_NAME :value: 'rocdl.raw.ptr.buffer.load.async.lds' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: rsrc() -> _ods_ir .. py:method:: ldsPtr() -> _ods_ir .. py:method:: size() -> _ods_ir[_ods_ir] .. py:method:: voffset() -> _ods_ir[_ods_ir] .. py:method:: soffset() -> _ods_ir[_ods_ir] .. py:method:: offset() -> _ods_ir[_ods_ir] .. py:method:: aux() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:class:: RawPtrBufferLoadAsyncLdsOpAdaptor(operands: list[Value], attributes: OpAttributeMap) RawPtrBufferLoadAsyncLdsOpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.raw.ptr.buffer.load.async.lds' .. py:method:: rsrc() -> _ods_ir .. py:method:: ldsPtr() -> _ods_ir .. py:method:: size() -> _ods_ir[_ods_ir] .. py:method:: voffset() -> _ods_ir[_ods_ir] .. py:method:: soffset() -> _ods_ir[_ods_ir] .. py:method:: offset() -> _ods_ir[_ods_ir] .. py:method:: aux() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:function:: raw_ptr_buffer_load_async_lds(rsrc: _ods_ir, lds_ptr: _ods_ir, size: _ods_ir[_ods_ir], voffset: _ods_ir[_ods_ir], soffset: _ods_ir[_ods_ir], offset: _ods_ir[_ods_ir], *, aux: Optional[Union[Any, _ods_ir]] = None, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> RawPtrBufferLoadAsyncLdsOp .. py:class:: RawPtrBufferLoadLdsOp(rsrc: _ods_ir, ldsPtr: _ods_ir, size: _ods_ir[_ods_ir], voffset: _ods_ir[_ods_ir], soffset: _ods_ir[_ods_ir], offset: _ods_ir[_ods_ir], *, aux: Optional[Union[Any, _ods_ir]] = None, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.raw.ptr.buffer.load.lds' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: rsrc() -> _ods_ir .. py:method:: ldsPtr() -> _ods_ir .. py:method:: size() -> _ods_ir[_ods_ir] .. py:method:: voffset() -> _ods_ir[_ods_ir] .. py:method:: soffset() -> _ods_ir[_ods_ir] .. py:method:: offset() -> _ods_ir[_ods_ir] .. py:method:: aux() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:class:: RawPtrBufferLoadLdsOpAdaptor(operands: list[Value], attributes: OpAttributeMap) RawPtrBufferLoadLdsOpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.raw.ptr.buffer.load.lds' .. py:method:: rsrc() -> _ods_ir .. py:method:: ldsPtr() -> _ods_ir .. py:method:: size() -> _ods_ir[_ods_ir] .. py:method:: voffset() -> _ods_ir[_ods_ir] .. py:method:: soffset() -> _ods_ir[_ods_ir] .. py:method:: offset() -> _ods_ir[_ods_ir] .. py:method:: aux() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:function:: raw_ptr_buffer_load_lds(rsrc: _ods_ir, lds_ptr: _ods_ir, size: _ods_ir[_ods_ir], voffset: _ods_ir[_ods_ir], soffset: _ods_ir[_ods_ir], offset: _ods_ir[_ods_ir], *, aux: Optional[Union[Any, _ods_ir]] = None, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> RawPtrBufferLoadLdsOp .. py:class:: RawPtrBufferLoadOp(res: _ods_ir, rsrc: _ods_ir, offset: _ods_ir[_ods_ir], soffset: _ods_ir[_ods_ir], *, aux: Optional[Union[Any, _ods_ir]] = None, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.raw.ptr.buffer.load' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: rsrc() -> _ods_ir .. py:method:: offset() -> _ods_ir[_ods_ir] .. py:method:: soffset() -> _ods_ir[_ods_ir] .. py:method:: aux() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:method:: res() -> _ods_ir .. py:class:: RawPtrBufferLoadOpAdaptor(operands: list[Value], attributes: OpAttributeMap) RawPtrBufferLoadOpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.raw.ptr.buffer.load' .. py:method:: rsrc() -> _ods_ir .. py:method:: offset() -> _ods_ir[_ods_ir] .. py:method:: soffset() -> _ods_ir[_ods_ir] .. py:method:: aux() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:function:: raw_ptr_buffer_load(res: _ods_ir, rsrc: _ods_ir, offset: _ods_ir[_ods_ir], soffset: _ods_ir[_ods_ir], *, aux: Optional[Union[Any, _ods_ir]] = None, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: RawPtrBufferStoreOp(vdata: _ods_ir, rsrc: _ods_ir, offset: _ods_ir[_ods_ir], soffset: _ods_ir[_ods_ir], *, aux: Optional[Union[Any, _ods_ir]] = None, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.raw.ptr.buffer.store' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: vdata() -> _ods_ir .. py:method:: rsrc() -> _ods_ir .. py:method:: offset() -> _ods_ir[_ods_ir] .. py:method:: soffset() -> _ods_ir[_ods_ir] .. py:method:: aux() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:class:: RawPtrBufferStoreOpAdaptor(operands: list[Value], attributes: OpAttributeMap) RawPtrBufferStoreOpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.raw.ptr.buffer.store' .. py:method:: vdata() -> _ods_ir .. py:method:: rsrc() -> _ods_ir .. py:method:: offset() -> _ods_ir[_ods_ir] .. py:method:: soffset() -> _ods_ir[_ods_ir] .. py:method:: aux() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:function:: raw_ptr_buffer_store(vdata: _ods_ir, rsrc: _ods_ir, offset: _ods_ir[_ods_ir], soffset: _ods_ir[_ods_ir], *, aux: Optional[Union[Any, _ods_ir]] = None, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> RawPtrBufferStoreOp .. py:class:: ReadfirstlaneOp(res: _ods_ir, src: _ods_ir, *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Returns the value in the lowest active lane of the input operand. Example: .. code:: mlir // Scalar readfirstlane. %0 = rocdl.readfirstlane %src0 : f32 // Vector readfirstlane. %1 = rocdl.readfirstlane %src1 : vector<2xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.readfirstlane' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: src() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: ReadfirstlaneOpAdaptor(operands: list[Value], attributes: OpAttributeMap) ReadfirstlaneOpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.readfirstlane' .. py:method:: src() -> _ods_ir .. py:function:: readfirstlane(res: _ods_ir, src: _ods_ir, *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: ReadlaneOp(res: _ods_ir, src0: _ods_ir, src1: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Get the value in lane ``src1`` from input ``src0``. Example: .. code:: mlir // Scalar readlane. %0 = rocdl.readlane %src0, %idx : (f32, i32) -> f32 // Vector readlane. %1 = rocdl.readlane %src1, %idx : (vector<2xf32>, i32) -> vector<2xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.readlane' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: src0() -> _ods_ir .. py:method:: src1() -> _ods_ir[_ods_ir] .. py:method:: res() -> _ods_ir .. py:class:: ReadlaneOpAdaptor(operands: list[Value], attributes: OpAttributeMap) ReadlaneOpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.readlane' .. py:method:: src0() -> _ods_ir .. py:method:: src1() -> _ods_ir[_ods_ir] .. py:function:: readlane(res: _ods_ir, src0: _ods_ir, src1: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: SBarrierOp(*, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Insert a workgroup barrier without memory fences. Available on gfx9 and later but deprecated on gfx12+; see ``rocdl.s.barrier.signal`` and ``rocdl.s.barrier.wait`` instead. Example: .. code:: mlir // Synchronize threads within a workgroup. rocdl.s.barrier .. py:attribute:: OPERATION_NAME :value: 'rocdl.s.barrier' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:class:: SBarrierOpAdaptor(operands: list[Value], attributes: OpAttributeMap) SBarrierOpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.s.barrier' .. py:function:: s_barrier(*, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> SBarrierOp .. py:class:: SNopOp(count: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Insert a number of NOP cycles. Example: .. code:: mlir // Insert a no-op. rocdl.s.nop 0 .. py:attribute:: OPERATION_NAME :value: 'rocdl.s.nop' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: count() -> _ods_ir .. py:class:: SNopOpAdaptor(operands: list[Value], attributes: OpAttributeMap) SNopOpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.s.nop' .. py:method:: count() -> _ods_ir .. py:function:: s_nop(count: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> SNopOp .. py:class:: SSleepOp(count: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Sleep for a number of clock cycles. Example: .. code:: mlir // Sleep for a minimum duration. rocdl.s.sleep 0 .. py:attribute:: OPERATION_NAME :value: 'rocdl.s.sleep' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: count() -> _ods_ir .. py:class:: SSleepOpAdaptor(operands: list[Value], attributes: OpAttributeMap) SSleepOpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.s.sleep' .. py:method:: count() -> _ods_ir .. py:function:: s_sleep(count: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> SSleepOp .. py:class:: SWaitcntOp(bitfield: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Wait for outstanding memory operations to complete, as specified by a bitfield whose semantics depend on the target chipset. Example: .. code:: mlir // Wait for all counters to reach zero. rocdl.s.waitcnt 0 .. py:attribute:: OPERATION_NAME :value: 'rocdl.s.waitcnt' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: bitfield() -> _ods_ir .. py:class:: SWaitcntOpAdaptor(operands: list[Value], attributes: OpAttributeMap) SWaitcntOpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.s.waitcnt' .. py:method:: bitfield() -> _ods_ir .. py:function:: s_waitcnt(bitfield: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> SWaitcntOp .. py:class:: SchedBarrier(mask: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Insert a scheduling barrier with the given mask. The mask is a bitfield that controls which instruction types may be scheduled across the barrier. The mask values mirror the ``llvm.amdgcn.sched.barrier`` intrinsic's documented mask values and the AMDGPU backend's ``SchedGroupMask`` enum. ``all_vmem`` and ``all_ds`` are supersets that also include LDSDMA instructions, while ``vmem_read``, ``vmem_write``, ``ds_read``, and ``ds_write`` do not. Example: .. code:: mlir // Scheduling barrier with no instructions allowed to cross. rocdl.sched.barrier none // Allow VALU and all VMEM instructions to cross. rocdl.sched.barrier valu|all_vmem .. py:attribute:: OPERATION_NAME :value: 'rocdl.sched.barrier' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: mask() -> _ods_ir .. py:class:: SchedBarrierAdaptor(operands: list[Value], attributes: OpAttributeMap) SchedBarrierAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.sched.barrier' .. py:method:: mask() -> _ods_ir .. py:function:: sched_barrier(mask: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> SchedBarrier .. py:class:: SchedGroupBarrier(mask: Union[Any, _ods_ir], size: Union[int, _ods_ir], groupId: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Insert a scheduling group barrier. The first parameter uses the same scheduling group mask values as ``rocdl.sched.barrier``. Example: .. code:: mlir // Schedule group barrier with mask, size, and group id. rocdl.sched.group.barrier mfma_wmma, 1, 0 .. py:attribute:: OPERATION_NAME :value: 'rocdl.sched.group.barrier' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: mask() -> _ods_ir .. py:method:: size() -> _ods_ir .. py:method:: groupId() -> _ods_ir .. py:class:: SchedGroupBarrierAdaptor(operands: list[Value], attributes: OpAttributeMap) SchedGroupBarrierAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.sched.group.barrier' .. py:method:: mask() -> _ods_ir .. py:method:: size() -> _ods_ir .. py:method:: groupId() -> _ods_ir .. py:function:: sched_group_barrier(mask: Union[Any, _ods_ir], size: Union[int, _ods_ir], group_id: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> SchedGroupBarrier .. py:class:: SetPrioOp(priority: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Set the wavefront scheduling priority. Example: .. code:: mlir // Set priority to 0. rocdl.s.setprio 0 .. py:attribute:: OPERATION_NAME :value: 'rocdl.s.setprio' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: priority() -> _ods_ir .. py:class:: SetPrioOpAdaptor(operands: list[Value], attributes: OpAttributeMap) SetPrioOpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.s.setprio' .. py:method:: priority() -> _ods_ir .. py:function:: s_setprio(priority: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> SetPrioOp .. py:class:: TensorLoadToLDSOp(dgroup0: _ods_ir[_ods_ir], dgroup1: _ods_ir[_ods_ir], dgroup2: _ods_ir[_ods_ir], dgroup3: _ods_ir[_ods_ir], dgroup4: _ods_ir[_ods_ir], *, cachePolicy: Optional[Union[Any, _ods_ir]] = None, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Moves tiles of tensor data between global memory and LDS. The tile is described by the $dgroup descriptors. 5 $dgroup descriptors allows for movement of up to 5D tensors. $cachePolicy describes the memory scope and an indicator of expected data re-use. This op is for gfx1250+ architectures. Example: .. code:: mlir // Tensor load from global memory to LDS using 4 descriptor groups. rocdl.tensor.load.to.lds %dg0, %dg1, %dg2, %dg3, %dg4, 0 : vector<4xi32>, vector<8xi32> // Tensor store from LDS to global memory using 4 descriptor groups. rocdl.tensor.store.from.lds %dg0, %dg1, %dg2, %dg3, %dg4, 0 : vector<4xi32>, vector<8xi32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.tensor.load.to.lds' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: dgroup0() -> _ods_ir[_ods_ir] .. py:method:: dgroup1() -> _ods_ir[_ods_ir] .. py:method:: dgroup2() -> _ods_ir[_ods_ir] .. py:method:: dgroup3() -> _ods_ir[_ods_ir] .. py:method:: dgroup4() -> _ods_ir[_ods_ir] .. py:method:: cachePolicy() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:class:: TensorLoadToLDSOpAdaptor(operands: list[Value], attributes: OpAttributeMap) TensorLoadToLDSOpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.tensor.load.to.lds' .. py:method:: dgroup0() -> _ods_ir[_ods_ir] .. py:method:: dgroup1() -> _ods_ir[_ods_ir] .. py:method:: dgroup2() -> _ods_ir[_ods_ir] .. py:method:: dgroup3() -> _ods_ir[_ods_ir] .. py:method:: dgroup4() -> _ods_ir[_ods_ir] .. py:method:: cachePolicy() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:function:: tensor_load_to_lds(dgroup0: _ods_ir[_ods_ir], dgroup1: _ods_ir[_ods_ir], dgroup2: _ods_ir[_ods_ir], dgroup3: _ods_ir[_ods_ir], dgroup4: _ods_ir[_ods_ir], *, cache_policy: Optional[Union[Any, _ods_ir]] = None, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> TensorLoadToLDSOp .. py:class:: TensorStoreFromLDSOp(dgroup0: _ods_ir[_ods_ir], dgroup1: _ods_ir[_ods_ir], dgroup2: _ods_ir[_ods_ir], dgroup3: _ods_ir[_ods_ir], dgroup4: _ods_ir[_ods_ir], *, cachePolicy: Optional[Union[Any, _ods_ir]] = None, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Moves tiles of tensor data between global memory and LDS. The tile is described by the $dgroup descriptors. 5 $dgroup descriptors allows for movement of up to 5D tensors. $cachePolicy describes the memory scope and an indicator of expected data re-use. This op is for gfx1250+ architectures. Example: .. code:: mlir // Tensor load from global memory to LDS using 4 descriptor groups. rocdl.tensor.load.to.lds %dg0, %dg1, %dg2, %dg3, %dg4, 0 : vector<4xi32>, vector<8xi32> // Tensor store from LDS to global memory using 4 descriptor groups. rocdl.tensor.store.from.lds %dg0, %dg1, %dg2, %dg3, %dg4, 0 : vector<4xi32>, vector<8xi32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.tensor.store.from.lds' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: dgroup0() -> _ods_ir[_ods_ir] .. py:method:: dgroup1() -> _ods_ir[_ods_ir] .. py:method:: dgroup2() -> _ods_ir[_ods_ir] .. py:method:: dgroup3() -> _ods_ir[_ods_ir] .. py:method:: dgroup4() -> _ods_ir[_ods_ir] .. py:method:: cachePolicy() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:class:: TensorStoreFromLDSOpAdaptor(operands: list[Value], attributes: OpAttributeMap) TensorStoreFromLDSOpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.tensor.store.from.lds' .. py:method:: dgroup0() -> _ods_ir[_ods_ir] .. py:method:: dgroup1() -> _ods_ir[_ods_ir] .. py:method:: dgroup2() -> _ods_ir[_ods_ir] .. py:method:: dgroup3() -> _ods_ir[_ods_ir] .. py:method:: dgroup4() -> _ods_ir[_ods_ir] .. py:method:: cachePolicy() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:function:: tensor_store_from_lds(dgroup0: _ods_ir[_ods_ir], dgroup1: _ods_ir[_ods_ir], dgroup2: _ods_ir[_ods_ir], dgroup3: _ods_ir[_ods_ir], dgroup4: _ods_ir[_ods_ir], *, cache_policy: Optional[Union[Any, _ods_ir]] = None, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> TensorStoreFromLDSOp .. py:class:: ThreadIdXOp(res: _ods_ir, *, range: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Read a hardware register for thread/workgroup/cluster identification. An optional ``range`` attribute can constrain the returned value. Example: .. code:: mlir // Read the workitem id in the x dimension. %0 = rocdl.workitem.id.x : i32 // Read with a known range constraint. %1 = rocdl.workitem.id.x range : i32 .. py:attribute:: OPERATION_NAME :value: 'rocdl.workitem.id.x' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: range() -> Optional[_ods_ir] .. py:method:: res() -> _ods_ir .. py:class:: ThreadIdXOpAdaptor(operands: list[Value], attributes: OpAttributeMap) ThreadIdXOpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.workitem.id.x' .. py:method:: range() -> Optional[_ods_ir] .. py:function:: workitem_id_x(res: _ods_ir, *, range: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: ThreadIdYOp(res: _ods_ir, *, range: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Read a hardware register for thread/workgroup/cluster identification. An optional ``range`` attribute can constrain the returned value. Example: .. code:: mlir // Read the workitem id in the x dimension. %0 = rocdl.workitem.id.x : i32 // Read with a known range constraint. %1 = rocdl.workitem.id.x range : i32 .. py:attribute:: OPERATION_NAME :value: 'rocdl.workitem.id.y' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: range() -> Optional[_ods_ir] .. py:method:: res() -> _ods_ir .. py:class:: ThreadIdYOpAdaptor(operands: list[Value], attributes: OpAttributeMap) ThreadIdYOpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.workitem.id.y' .. py:method:: range() -> Optional[_ods_ir] .. py:function:: workitem_id_y(res: _ods_ir, *, range: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: ThreadIdZOp(res: _ods_ir, *, range: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Read a hardware register for thread/workgroup/cluster identification. An optional ``range`` attribute can constrain the returned value. Example: .. code:: mlir // Read the workitem id in the x dimension. %0 = rocdl.workitem.id.x : i32 // Read with a known range constraint. %1 = rocdl.workitem.id.x range : i32 .. py:attribute:: OPERATION_NAME :value: 'rocdl.workitem.id.z' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: range() -> Optional[_ods_ir] .. py:method:: res() -> _ods_ir .. py:class:: ThreadIdZOpAdaptor(operands: list[Value], attributes: OpAttributeMap) ThreadIdZOpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.workitem.id.z' .. py:method:: range() -> Optional[_ods_ir] .. py:function:: workitem_id_z(res: _ods_ir, *, range: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: WaitAsynccntOp(count: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Wait for the counter specified to be less-than or equal-to the ``count`` before continuing. Available on gfx1250+. Example: .. code:: mlir // Wait for async counter to drain. rocdl.s.wait.asynccnt 0 .. py:attribute:: OPERATION_NAME :value: 'rocdl.s.wait.asynccnt' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: count() -> _ods_ir .. py:class:: WaitAsynccntOpAdaptor(operands: list[Value], attributes: OpAttributeMap) WaitAsynccntOpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.s.wait.asynccnt' .. py:method:: count() -> _ods_ir .. py:function:: s_wait_asynccnt(count: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> WaitAsynccntOp .. py:class:: WaitAsyncmarkOp(count: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` This operation, along with ``rocdl.asyncmark``, forms the compiler-provided framework for explicitly tracking asynchronous operations. At the point where a wait.asyncmark operation is executed, all async operations that were parts of any async group (established by asyncmark in program order) other than the ``count`` previously-added ones will have finished executing. For more detail, including on how this mechanism composes with function calls, see `the LLVM documentation on async tracking `_. Available on gfx9 and later. Example: .. code:: mlir // Wait until at most N async groups remain outstanding. rocdl.wait.asyncmark 1 Usage example: .. code:: mlir rocdl.tensor.load.to.lds ... rocdl.global.async.load.to.lds ... rocdl.asyncmark rocdl.tensor.load.to.lds ... rocdl.global.async.load.to.lds ... rocdl.asyncmark rocdl.wait.asyncmark 1 // First group of loads completes after this .. py:attribute:: OPERATION_NAME :value: 'rocdl.wait.asyncmark' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: count() -> _ods_ir .. py:class:: WaitAsyncmarkOpAdaptor(operands: list[Value], attributes: OpAttributeMap) WaitAsyncmarkOpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.wait.asyncmark' .. py:method:: count() -> _ods_ir .. py:function:: wait_asyncmark(count: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> WaitAsyncmarkOp .. py:class:: WaitDscntOp(count: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Wait for the counter specified to be less-than or equal-to the ``count`` before continuing. Available on gfx12+. Example: .. code:: mlir // Wait for data-sharing counter to drain. rocdl.s.wait.dscnt 0 .. py:attribute:: OPERATION_NAME :value: 'rocdl.s.wait.dscnt' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: count() -> _ods_ir .. py:class:: WaitDscntOpAdaptor(operands: list[Value], attributes: OpAttributeMap) WaitDscntOpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.s.wait.dscnt' .. py:method:: count() -> _ods_ir .. py:function:: s_wait_dscnt(count: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> WaitDscntOp .. py:class:: WaitExpcntOp(count: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Wait for the counter specified to be less-than or equal-to the ``count`` before continuing. Available on gfx12+. Example: .. code:: mlir // Wait for export counter to drain. rocdl.s.wait.expcnt 0 .. py:attribute:: OPERATION_NAME :value: 'rocdl.s.wait.expcnt' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: count() -> _ods_ir .. py:class:: WaitExpcntOpAdaptor(operands: list[Value], attributes: OpAttributeMap) WaitExpcntOpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.s.wait.expcnt' .. py:method:: count() -> _ods_ir .. py:function:: s_wait_expcnt(count: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> WaitExpcntOp .. py:class:: WaitLoadcntOp(count: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Wait for the counter specified to be less-than or equal-to the ``count`` before continuing. Available on gfx12+. Example: .. code:: mlir // Wait for load counter to drain. rocdl.s.wait.loadcnt 0 .. py:attribute:: OPERATION_NAME :value: 'rocdl.s.wait.loadcnt' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: count() -> _ods_ir .. py:class:: WaitLoadcntOpAdaptor(operands: list[Value], attributes: OpAttributeMap) WaitLoadcntOpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.s.wait.loadcnt' .. py:method:: count() -> _ods_ir .. py:function:: s_wait_loadcnt(count: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> WaitLoadcntOp .. py:class:: WaitStorecntOp(count: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Wait for the counter specified to be less-than or equal-to the ``count`` before continuing. Available on gfx12+. Example: .. code:: mlir // Wait for store counter to drain. rocdl.s.wait.storecnt 0 .. py:attribute:: OPERATION_NAME :value: 'rocdl.s.wait.storecnt' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: count() -> _ods_ir .. py:class:: WaitStorecntOpAdaptor(operands: list[Value], attributes: OpAttributeMap) WaitStorecntOpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.s.wait.storecnt' .. py:method:: count() -> _ods_ir .. py:function:: s_wait_storecnt(count: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> WaitStorecntOp .. py:class:: WaitTensorcntOp(count: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Wait for the counter specified to be less-than or equal-to the ``count`` before continuing. Available on gfx1250+. Example: .. code:: mlir // Wait for tensor counter to drain. rocdl.s.wait.tensorcnt 0 .. py:attribute:: OPERATION_NAME :value: 'rocdl.s.wait.tensorcnt' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: count() -> _ods_ir .. py:class:: WaitTensorcntOpAdaptor(operands: list[Value], attributes: OpAttributeMap) WaitTensorcntOpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.s.wait.tensorcnt' .. py:method:: count() -> _ods_ir .. py:function:: s_wait_tensorcnt(count: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> WaitTensorcntOp .. py:class:: WakeupBarrierOp(ptr: _ods_ir, *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Wakes up waves associated with a given named barrier. Note, This op does not release waves waiting at the barrier. It just signal other waves in the same work-group waiting on the indicated named barrier to wake up. Available on gfx1250+. Example: .. code:: mlir // Wake up waves waiting on a named barrier. rocdl.s.wakeup.barrier %ptr : !llvm.ptr<3> .. py:attribute:: OPERATION_NAME :value: 'rocdl.s.wakeup.barrier' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: ptr() -> _ods_ir .. py:class:: WakeupBarrierOpAdaptor(operands: list[Value], attributes: OpAttributeMap) WakeupBarrierOpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.s.wakeup.barrier' .. py:method:: ptr() -> _ods_ir .. py:function:: s_wakeup_barrier(ptr: _ods_ir, *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> WakeupBarrierOp .. py:class:: WaveBarrierOp(*, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Insert a wave-level (subgroup) barrier. Synchronizes lanes within a single wave/wavefront without any memory ordering guarantees. Example: .. code:: mlir rocdl.wave.barrier .. py:attribute:: OPERATION_NAME :value: 'rocdl.wave.barrier' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:class:: WaveBarrierOpAdaptor(operands: list[Value], attributes: OpAttributeMap) WaveBarrierOpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.wave.barrier' .. py:function:: wave_barrier(*, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> WaveBarrierOp .. py:class:: WaveId(res: _ods_ir, *, range: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Read a hardware register for thread/workgroup/cluster identification. An optional ``range`` attribute can constrain the returned value. Example: .. code:: mlir // Read the workitem id in the x dimension. %0 = rocdl.workitem.id.x : i32 // Read with a known range constraint. %1 = rocdl.workitem.id.x range : i32 .. py:attribute:: OPERATION_NAME :value: 'rocdl.wave.id' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: range() -> Optional[_ods_ir] .. py:method:: res() -> _ods_ir .. py:class:: WaveIdAdaptor(operands: list[Value], attributes: OpAttributeMap) WaveIdAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.wave.id' .. py:method:: range() -> Optional[_ods_ir] .. py:function:: wave_id(res: _ods_ir, *, range: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: WavefrontSizeOp(res: _ods_ir, *, range: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Read a hardware register for thread/workgroup/cluster identification. An optional ``range`` attribute can constrain the returned value. Example: .. code:: mlir // Read the workitem id in the x dimension. %0 = rocdl.workitem.id.x : i32 // Read with a known range constraint. %1 = rocdl.workitem.id.x range : i32 .. py:attribute:: OPERATION_NAME :value: 'rocdl.wavefrontsize' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: range() -> Optional[_ods_ir] .. py:method:: res() -> _ods_ir .. py:class:: WavefrontSizeOpAdaptor(operands: list[Value], attributes: OpAttributeMap) WavefrontSizeOpAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.wavefrontsize' .. py:method:: range() -> Optional[_ods_ir] .. py:function:: wavefrontsize(res: _ods_ir, *, range: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: dot4_f32_bf8_bf8(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Packed intra-lane dot-product with no clamp control. Computes ``res = sum_i a[i]*b[i] + c``. Covers the full-f16/bf16 accumulator forms (``fdot2.f16.f16``, ``fdot2.bf16.bf16``) and the FP8/BF8 ``dot4.f32.*`` variants, whose hardware instructions have no CLAMP bit in their modifier word. Example: .. code:: mlir %r = rocdl.dot4.f32.bf8.bf8 %a, %b, %c : (i32, i32, f32) -> f32 .. py:attribute:: OPERATION_NAME :value: 'rocdl.dot4.f32.bf8.bf8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: dot4_f32_bf8_bf8Adaptor(operands: list[Value], attributes: OpAttributeMap) dot4_f32_bf8_bf8Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.dot4.f32.bf8.bf8' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:function:: dot4_f32_bf8_bf8_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: dot4_f32_bf8_fp8(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Packed intra-lane dot-product with no clamp control. Computes ``res = sum_i a[i]*b[i] + c``. Covers the full-f16/bf16 accumulator forms (``fdot2.f16.f16``, ``fdot2.bf16.bf16``) and the FP8/BF8 ``dot4.f32.*`` variants, whose hardware instructions have no CLAMP bit in their modifier word. Example: .. code:: mlir %r = rocdl.dot4.f32.bf8.fp8 %a, %b, %c : (i32, i32, f32) -> f32 .. py:attribute:: OPERATION_NAME :value: 'rocdl.dot4.f32.bf8.fp8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: dot4_f32_bf8_fp8Adaptor(operands: list[Value], attributes: OpAttributeMap) dot4_f32_bf8_fp8Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.dot4.f32.bf8.fp8' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:function:: dot4_f32_bf8_fp8_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: dot4_f32_fp8_bf8(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Packed intra-lane dot-product with no clamp control. Computes ``res = sum_i a[i]*b[i] + c``. Covers the full-f16/bf16 accumulator forms (``fdot2.f16.f16``, ``fdot2.bf16.bf16``) and the FP8/BF8 ``dot4.f32.*`` variants, whose hardware instructions have no CLAMP bit in their modifier word. Example: .. code:: mlir %r = rocdl.dot4.f32.fp8.bf8 %a, %b, %c : (i32, i32, f32) -> f32 .. py:attribute:: OPERATION_NAME :value: 'rocdl.dot4.f32.fp8.bf8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: dot4_f32_fp8_bf8Adaptor(operands: list[Value], attributes: OpAttributeMap) dot4_f32_fp8_bf8Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.dot4.f32.fp8.bf8' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:function:: dot4_f32_fp8_bf8_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: dot4_f32_fp8_fp8(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Packed intra-lane dot-product with no clamp control. Computes ``res = sum_i a[i]*b[i] + c``. Covers the full-f16/bf16 accumulator forms (``fdot2.f16.f16``, ``fdot2.bf16.bf16``) and the FP8/BF8 ``dot4.f32.*`` variants, whose hardware instructions have no CLAMP bit in their modifier word. Example: .. code:: mlir %r = rocdl.dot4.f32.fp8.fp8 %a, %b, %c : (i32, i32, f32) -> f32 .. py:attribute:: OPERATION_NAME :value: 'rocdl.dot4.f32.fp8.fp8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: dot4_f32_fp8_fp8Adaptor(operands: list[Value], attributes: OpAttributeMap) dot4_f32_fp8_fp8Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.dot4.f32.fp8.fp8' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:function:: dot4_f32_fp8_fp8_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: ds_read_tr4_b64(res: _ods_ir, ptr: _ods_ir, *, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.ds.read.tr4.b64' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: ptr() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:method:: res() -> _ods_ir .. py:class:: ds_read_tr4_b64Adaptor(operands: list[Value], attributes: OpAttributeMap) ds_read_tr4_b64Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.ds.read.tr4.b64' .. py:method:: ptr() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:function:: ds_read_tr4_b64_(res: _ods_ir, ptr: _ods_ir, *, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: ds_read_tr6_b96(res: _ods_ir, ptr: _ods_ir, *, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.ds.read.tr6.b96' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: ptr() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:method:: res() -> _ods_ir .. py:class:: ds_read_tr6_b96Adaptor(operands: list[Value], attributes: OpAttributeMap) ds_read_tr6_b96Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.ds.read.tr6.b96' .. py:method:: ptr() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:function:: ds_read_tr6_b96_(res: _ods_ir, ptr: _ods_ir, *, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: ds_read_tr8_b64(res: _ods_ir, ptr: _ods_ir, *, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.ds.read.tr8.b64' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: ptr() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:method:: res() -> _ods_ir .. py:class:: ds_read_tr8_b64Adaptor(operands: list[Value], attributes: OpAttributeMap) ds_read_tr8_b64Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.ds.read.tr8.b64' .. py:method:: ptr() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:function:: ds_read_tr8_b64_(res: _ods_ir, ptr: _ods_ir, *, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: ds_read_tr16_b64(res: _ods_ir, ptr: _ods_ir, *, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.ds.read.tr16.b64' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: ptr() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:method:: res() -> _ods_ir .. py:class:: ds_read_tr16_b64Adaptor(operands: list[Value], attributes: OpAttributeMap) ds_read_tr16_b64Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.ds.read.tr16.b64' .. py:method:: ptr() -> _ods_ir .. py:method:: alias_scopes() -> Optional[_ods_ir] .. py:method:: noalias_scopes() -> Optional[_ods_ir] .. py:method:: tbaa() -> Optional[_ods_ir] .. py:function:: ds_read_tr16_b64_(res: _ods_ir, ptr: _ods_ir, *, alias_scopes: Optional[Union[Any, _ods_ir]] = None, noalias_scopes: Optional[Union[Any, _ods_ir]] = None, tbaa: Optional[Union[Any, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: fdot2(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir, *, clamp: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Packed intra-lane dot-product with optional result clamping (``clamp``). Computes ``res = sum_i a[i]*b[i] + c``, where ``a`` and ``b`` hold packed 4/8/16-bit data (for ``dot2``,``dot4``,``dot8``). Example: .. code:: mlir %r = rocdl.fdot2 %a, %b, %c {clamp = true} : (vector<2xf16>, vector<2xf16>, f32) -> f32 .. py:attribute:: OPERATION_NAME :value: 'rocdl.fdot2' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir .. py:method:: clamp() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: fdot2Adaptor(operands: list[Value], attributes: OpAttributeMap) fdot2Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.fdot2' .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir .. py:method:: clamp() -> _ods_ir .. py:function:: fdot2_(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir, *, clamp: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: fdot2_bf16_bf16(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir, *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Packed intra-lane dot-product with no clamp control. Computes ``res = sum_i a[i]*b[i] + c``. Covers the full-f16/bf16 accumulator forms (``fdot2.f16.f16``, ``fdot2.bf16.bf16``) and the FP8/BF8 ``dot4.f32.*`` variants, whose hardware instructions have no CLAMP bit in their modifier word. Example: .. code:: mlir %r = rocdl.fdot2.bf16.bf16 %a, %b, %c : (vector<2xbf16>, vector<2xbf16>, bf16) -> bf16 .. py:attribute:: OPERATION_NAME :value: 'rocdl.fdot2.bf16.bf16' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: fdot2_bf16_bf16Adaptor(operands: list[Value], attributes: OpAttributeMap) fdot2_bf16_bf16Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.fdot2.bf16.bf16' .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir .. py:function:: fdot2_bf16_bf16_(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir, *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: fdot2_f16_f16(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir, *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Packed intra-lane dot-product with no clamp control. Computes ``res = sum_i a[i]*b[i] + c``. Covers the full-f16/bf16 accumulator forms (``fdot2.f16.f16``, ``fdot2.bf16.bf16``) and the FP8/BF8 ``dot4.f32.*`` variants, whose hardware instructions have no CLAMP bit in their modifier word. Example: .. code:: mlir %r = rocdl.fdot2.f16.f16 %a, %b, %c : (vector<2xf16>, vector<2xf16>, f16) -> f16 .. py:attribute:: OPERATION_NAME :value: 'rocdl.fdot2.f16.f16' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: fdot2_f16_f16Adaptor(operands: list[Value], attributes: OpAttributeMap) fdot2_f16_f16Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.fdot2.f16.f16' .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir .. py:function:: fdot2_f16_f16_(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir, *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: fdot2_f32_bf16(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir, *, clamp: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Packed intra-lane dot-product with optional result clamping (``clamp``). Computes ``res = sum_i a[i]*b[i] + c``, where ``a`` and ``b`` hold packed 4/8/16-bit data (for ``dot2``,``dot4``,``dot8``). Example: .. code:: mlir %r = rocdl.fdot2.f32.bf16 %a, %b, %c {clamp = true} : (vector<2xbf16>, vector<2xbf16>, f32) -> f32 .. py:attribute:: OPERATION_NAME :value: 'rocdl.fdot2.f32.bf16' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir .. py:method:: clamp() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: fdot2_f32_bf16Adaptor(operands: list[Value], attributes: OpAttributeMap) fdot2_f32_bf16Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.fdot2.f32.bf16' .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir .. py:method:: clamp() -> _ods_ir .. py:function:: fdot2_f32_bf16_(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir, *, clamp: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: mfma_f32_4x4x1f32(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Matrix fused multiply-add (MFMA) intrinsic. Computes ``D = A * B + C`` with matrix operands. The ``cbsz``, ``abid``, and ``blgp`` attributes control broadcast and block layout modes. Example: .. code:: mlir %r0 = mfma.f32.4x4x1f32 %a0, %b0, %c0, 0, 0, none : (f32, f32, vector<4xf32>) -> vector<4xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.f32.4x4x1f32' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: mfma_f32_4x4x1f32Adaptor(operands: list[Value], attributes: OpAttributeMap) mfma_f32_4x4x1f32Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.f32.4x4x1f32' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:function:: mfma_f32_4x4x1f32_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: mfma_f32_4x4x2bf16(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Matrix fused multiply-add (MFMA) intrinsic. Computes ``D = A * B + C`` with matrix operands. The ``cbsz``, ``abid``, and ``blgp`` attributes control broadcast and block layout modes. Example: .. code:: mlir %r0 = mfma.f32.4x4x2bf16 %a0, %b0, %c0, 0, 0, none : (vector<2xi16>, vector<2xi16>, vector<4xf32>) -> vector<4xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.f32.4x4x2bf16' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: mfma_f32_4x4x2bf16Adaptor(operands: list[Value], attributes: OpAttributeMap) mfma_f32_4x4x2bf16Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.f32.4x4x2bf16' .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:function:: mfma_f32_4x4x2bf16_(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: mfma_f32_4x4x4bf16_1k(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Matrix fused multiply-add (MFMA) intrinsic. Computes ``D = A * B + C`` with matrix operands. The ``cbsz``, ``abid``, and ``blgp`` attributes control broadcast and block layout modes. Example: .. code:: mlir %r0 = mfma.f32.4x4x4bf16.1k %a0, %b0, %c0, 0, 0, none : (vector<4xi16>, vector<4xi16>, vector<4xf32>) -> vector<4xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.f32.4x4x4bf16.1k' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: mfma_f32_4x4x4bf16_1kAdaptor(operands: list[Value], attributes: OpAttributeMap) mfma_f32_4x4x4bf16_1kAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.f32.4x4x4bf16.1k' .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:function:: mfma_f32_4x4x4bf16_1k_(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: mfma_f32_4x4x4f16(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Matrix fused multiply-add (MFMA) intrinsic. Computes ``D = A * B + C`` with matrix operands. The ``cbsz``, ``abid``, and ``blgp`` attributes control broadcast and block layout modes. Example: .. code:: mlir %r0 = mfma.f32.4x4x4f16 %a0, %b0, %c0, 0, 0, none : (vector<4xf16>, vector<4xf16>, vector<4xf32>) -> vector<4xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.f32.4x4x4f16' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: mfma_f32_4x4x4f16Adaptor(operands: list[Value], attributes: OpAttributeMap) mfma_f32_4x4x4f16Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.f32.4x4x4f16' .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:function:: mfma_f32_4x4x4f16_(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: mfma_f32_16x16x1f32(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Matrix fused multiply-add (MFMA) intrinsic. Computes ``D = A * B + C`` with matrix operands. The ``cbsz``, ``abid``, and ``blgp`` attributes control broadcast and block layout modes. Example: .. code:: mlir %r0 = mfma.f32.16x16x1f32 %a0, %b0, %c0, 0, 0, none : (f32, f32, vector<16xf32>) -> vector<16xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.f32.16x16x1f32' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: mfma_f32_16x16x1f32Adaptor(operands: list[Value], attributes: OpAttributeMap) mfma_f32_16x16x1f32Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.f32.16x16x1f32' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:function:: mfma_f32_16x16x1f32_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: mfma_f32_16x16x2bf16(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Matrix fused multiply-add (MFMA) intrinsic. Computes ``D = A * B + C`` with matrix operands. The ``cbsz``, ``abid``, and ``blgp`` attributes control broadcast and block layout modes. Example: .. code:: mlir %r0 = mfma.f32.16x16x2bf16 %a0, %b0, %c0, 0, 0, none : (vector<2xi16>, vector<2xi16>, vector<16xf32>) -> vector<16xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.f32.16x16x2bf16' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: mfma_f32_16x16x2bf16Adaptor(operands: list[Value], attributes: OpAttributeMap) mfma_f32_16x16x2bf16Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.f32.16x16x2bf16' .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:function:: mfma_f32_16x16x2bf16_(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: mfma_f32_16x16x4bf16_1k(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Matrix fused multiply-add (MFMA) intrinsic. Computes ``D = A * B + C`` with matrix operands. The ``cbsz``, ``abid``, and ``blgp`` attributes control broadcast and block layout modes. Example: .. code:: mlir %r0 = mfma.f32.16x16x4bf16.1k %a0, %b0, %c0, 0, 0, none : (vector<4xi16>, vector<4xi16>, vector<16xf32>) -> vector<16xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.f32.16x16x4bf16.1k' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: mfma_f32_16x16x4bf16_1kAdaptor(operands: list[Value], attributes: OpAttributeMap) mfma_f32_16x16x4bf16_1kAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.f32.16x16x4bf16.1k' .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:function:: mfma_f32_16x16x4bf16_1k_(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: mfma_f32_16x16x4f16(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Matrix fused multiply-add (MFMA) intrinsic. Computes ``D = A * B + C`` with matrix operands. The ``cbsz``, ``abid``, and ``blgp`` attributes control broadcast and block layout modes. Example: .. code:: mlir %r0 = mfma.f32.16x16x4f16 %a0, %b0, %c0, 0, 0, none : (vector<4xf16>, vector<4xf16>, vector<16xf32>) -> vector<16xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.f32.16x16x4f16' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: mfma_f32_16x16x4f16Adaptor(operands: list[Value], attributes: OpAttributeMap) mfma_f32_16x16x4f16Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.f32.16x16x4f16' .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:function:: mfma_f32_16x16x4f16_(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: mfma_f32_16x16x4f32(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Matrix fused multiply-add (MFMA) intrinsic. Computes ``D = A * B + C`` with matrix operands. The ``cbsz``, ``abid``, and ``blgp`` attributes control broadcast and block layout modes. Example: .. code:: mlir %r0 = mfma.f32.16x16x4f32 %a0, %b0, %c0, 0, 0, none : (f32, f32, vector<4xf32>) -> vector<4xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.f32.16x16x4f32' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: mfma_f32_16x16x4f32Adaptor(operands: list[Value], attributes: OpAttributeMap) mfma_f32_16x16x4f32Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.f32.16x16x4f32' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:function:: mfma_f32_16x16x4f32_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: mfma_f32_16x16x8_xf32(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Matrix fused multiply-add (MFMA) intrinsic. Computes ``D = A * B + C`` with matrix operands. The ``cbsz``, ``abid``, and ``blgp`` attributes control broadcast and block layout modes. Example: .. code:: mlir %r0 = mfma.f32.16x16x8.xf32 %a0, %b0, %c0, 0, 0, none : (vector<2xf32>, vector<2xf32>, vector<4xf32>) -> vector<4xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.f32.16x16x8.xf32' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: mfma_f32_16x16x8_xf32Adaptor(operands: list[Value], attributes: OpAttributeMap) mfma_f32_16x16x8_xf32Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.f32.16x16x8.xf32' .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:function:: mfma_f32_16x16x8_xf32_(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: mfma_f32_16x16x8bf16(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Matrix fused multiply-add (MFMA) intrinsic. Computes ``D = A * B + C`` with matrix operands. The ``cbsz``, ``abid``, and ``blgp`` attributes control broadcast and block layout modes. Example: .. code:: mlir %r0 = mfma.f32.16x16x8bf16 %a0, %b0, %c0, 0, 0, none : (vector<2xi16>, vector<2xi16>, vector<4xf32>) -> vector<4xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.f32.16x16x8bf16' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: mfma_f32_16x16x8bf16Adaptor(operands: list[Value], attributes: OpAttributeMap) mfma_f32_16x16x8bf16Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.f32.16x16x8bf16' .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:function:: mfma_f32_16x16x8bf16_(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: mfma_f32_16x16x16bf16_1k(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Matrix fused multiply-add (MFMA) intrinsic. Computes ``D = A * B + C`` with matrix operands. The ``cbsz``, ``abid``, and ``blgp`` attributes control broadcast and block layout modes. Example: .. code:: mlir %r0 = mfma.f32.16x16x16bf16.1k %a0, %b0, %c0, 0, 0, none : (vector<4xi16>, vector<4xi16>, vector<4xf32>) -> vector<4xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.f32.16x16x16bf16.1k' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: mfma_f32_16x16x16bf16_1kAdaptor(operands: list[Value], attributes: OpAttributeMap) mfma_f32_16x16x16bf16_1kAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.f32.16x16x16bf16.1k' .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:function:: mfma_f32_16x16x16bf16_1k_(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: mfma_f32_16x16x16f16(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Matrix fused multiply-add (MFMA) intrinsic. Computes ``D = A * B + C`` with matrix operands. The ``cbsz``, ``abid``, and ``blgp`` attributes control broadcast and block layout modes. Example: .. code:: mlir %r0 = mfma.f32.16x16x16f16 %a0, %b0, %c0, 0, 0, none : (vector<4xf16>, vector<4xf16>, vector<4xf32>) -> vector<4xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.f32.16x16x16f16' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: mfma_f32_16x16x16f16Adaptor(operands: list[Value], attributes: OpAttributeMap) mfma_f32_16x16x16f16Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.f32.16x16x16f16' .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:function:: mfma_f32_16x16x16f16_(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: mfma_f32_16x16x32_bf8_bf8(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Matrix fused multiply-add (MFMA) intrinsic. Computes ``D = A * B + C`` with matrix operands. The ``cbsz``, ``abid``, and ``blgp`` attributes control broadcast and block layout modes. Example: .. code:: mlir %r0 = mfma.f32.16x16x32.bf8.bf8 %a0, %b0, %c0, 0, 0, none : (i64, i64, vector<4xf32>) -> vector<4xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.f32.16x16x32.bf8.bf8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: mfma_f32_16x16x32_bf8_bf8Adaptor(operands: list[Value], attributes: OpAttributeMap) mfma_f32_16x16x32_bf8_bf8Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.f32.16x16x32.bf8.bf8' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:function:: mfma_f32_16x16x32_bf8_bf8_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: mfma_f32_16x16x32_bf8_fp8(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Matrix fused multiply-add (MFMA) intrinsic. Computes ``D = A * B + C`` with matrix operands. The ``cbsz``, ``abid``, and ``blgp`` attributes control broadcast and block layout modes. Example: .. code:: mlir %r0 = mfma.f32.16x16x32.bf8.fp8 %a0, %b0, %c0, 0, 0, none : (i64, i64, vector<4xf32>) -> vector<4xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.f32.16x16x32.bf8.fp8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: mfma_f32_16x16x32_bf8_fp8Adaptor(operands: list[Value], attributes: OpAttributeMap) mfma_f32_16x16x32_bf8_fp8Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.f32.16x16x32.bf8.fp8' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:function:: mfma_f32_16x16x32_bf8_fp8_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: mfma_f32_16x16x32_bf16(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Matrix fused multiply-add (MFMA) intrinsic. Computes ``D = A * B + C`` with matrix operands. The ``cbsz``, ``abid``, and ``blgp`` attributes control broadcast and block layout modes. Example: .. code:: mlir %r0 = mfma.f32.16x16x32.bf16 %a0, %b0, %c0, 0, 0, none : (vector<8xbf16>, vector<8xbf16>, vector<4xf32>) -> vector<4xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.f32.16x16x32.bf16' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: mfma_f32_16x16x32_bf16Adaptor(operands: list[Value], attributes: OpAttributeMap) mfma_f32_16x16x32_bf16Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.f32.16x16x32.bf16' .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:function:: mfma_f32_16x16x32_bf16_(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: mfma_f32_16x16x32_f16(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Matrix fused multiply-add (MFMA) intrinsic. Computes ``D = A * B + C`` with matrix operands. The ``cbsz``, ``abid``, and ``blgp`` attributes control broadcast and block layout modes. Example: .. code:: mlir %r0 = mfma.f32.16x16x32.f16 %a0, %b0, %c0, 0, 0, none : (vector<8xf16>, vector<8xf16>, vector<4xf32>) -> vector<4xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.f32.16x16x32.f16' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: mfma_f32_16x16x32_f16Adaptor(operands: list[Value], attributes: OpAttributeMap) mfma_f32_16x16x32_f16Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.f32.16x16x32.f16' .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:function:: mfma_f32_16x16x32_f16_(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: mfma_f32_16x16x32_fp8_bf8(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Matrix fused multiply-add (MFMA) intrinsic. Computes ``D = A * B + C`` with matrix operands. The ``cbsz``, ``abid``, and ``blgp`` attributes control broadcast and block layout modes. Example: .. code:: mlir %r0 = mfma.f32.16x16x32.fp8.bf8 %a0, %b0, %c0, 0, 0, none : (i64, i64, vector<4xf32>) -> vector<4xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.f32.16x16x32.fp8.bf8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: mfma_f32_16x16x32_fp8_bf8Adaptor(operands: list[Value], attributes: OpAttributeMap) mfma_f32_16x16x32_fp8_bf8Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.f32.16x16x32.fp8.bf8' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:function:: mfma_f32_16x16x32_fp8_bf8_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: mfma_f32_16x16x32_fp8_fp8(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Matrix fused multiply-add (MFMA) intrinsic. Computes ``D = A * B + C`` with matrix operands. The ``cbsz``, ``abid``, and ``blgp`` attributes control broadcast and block layout modes. Example: .. code:: mlir %r0 = mfma.f32.16x16x32.fp8.fp8 %a0, %b0, %c0, 0, 0, none : (i64, i64, vector<4xf32>) -> vector<4xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.f32.16x16x32.fp8.fp8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: mfma_f32_16x16x32_fp8_fp8Adaptor(operands: list[Value], attributes: OpAttributeMap) mfma_f32_16x16x32_fp8_fp8Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.f32.16x16x32.fp8.fp8' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:function:: mfma_f32_16x16x32_fp8_fp8_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: mfma_f32_32x32x1f32(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Matrix fused multiply-add (MFMA) intrinsic. Computes ``D = A * B + C`` with matrix operands. The ``cbsz``, ``abid``, and ``blgp`` attributes control broadcast and block layout modes. Example: .. code:: mlir %r0 = mfma.f32.32x32x1f32 %a0, %b0, %c0, 0, 0, none : (f32, f32, vector<32xf32>) -> vector<32xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.f32.32x32x1f32' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: mfma_f32_32x32x1f32Adaptor(operands: list[Value], attributes: OpAttributeMap) mfma_f32_32x32x1f32Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.f32.32x32x1f32' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:function:: mfma_f32_32x32x1f32_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: mfma_f32_32x32x2bf16(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Matrix fused multiply-add (MFMA) intrinsic. Computes ``D = A * B + C`` with matrix operands. The ``cbsz``, ``abid``, and ``blgp`` attributes control broadcast and block layout modes. Example: .. code:: mlir %r0 = mfma.f32.32x32x2bf16 %a0, %b0, %c0, 0, 0, none : (vector<2xi16>, vector<2xi16>, vector<32xf32>) -> vector<32xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.f32.32x32x2bf16' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: mfma_f32_32x32x2bf16Adaptor(operands: list[Value], attributes: OpAttributeMap) mfma_f32_32x32x2bf16Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.f32.32x32x2bf16' .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:function:: mfma_f32_32x32x2bf16_(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: mfma_f32_32x32x2f32(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Matrix fused multiply-add (MFMA) intrinsic. Computes ``D = A * B + C`` with matrix operands. The ``cbsz``, ``abid``, and ``blgp`` attributes control broadcast and block layout modes. Example: .. code:: mlir %r0 = mfma.f32.32x32x2f32 %a0, %b0, %c0, 0, 0, none : (f32, f32, vector<16xf32>) -> vector<16xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.f32.32x32x2f32' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: mfma_f32_32x32x2f32Adaptor(operands: list[Value], attributes: OpAttributeMap) mfma_f32_32x32x2f32Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.f32.32x32x2f32' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:function:: mfma_f32_32x32x2f32_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: mfma_f32_32x32x4_xf32(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Matrix fused multiply-add (MFMA) intrinsic. Computes ``D = A * B + C`` with matrix operands. The ``cbsz``, ``abid``, and ``blgp`` attributes control broadcast and block layout modes. Example: .. code:: mlir %r0 = mfma.f32.32x32x4.xf32 %a0, %b0, %c0, 0, 0, none : (vector<2xf32>, vector<2xf32>, vector<16xf32>) -> vector<16xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.f32.32x32x4.xf32' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: mfma_f32_32x32x4_xf32Adaptor(operands: list[Value], attributes: OpAttributeMap) mfma_f32_32x32x4_xf32Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.f32.32x32x4.xf32' .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:function:: mfma_f32_32x32x4_xf32_(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: mfma_f32_32x32x4bf16(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Matrix fused multiply-add (MFMA) intrinsic. Computes ``D = A * B + C`` with matrix operands. The ``cbsz``, ``abid``, and ``blgp`` attributes control broadcast and block layout modes. Example: .. code:: mlir %r0 = mfma.f32.32x32x4bf16 %a0, %b0, %c0, 0, 0, none : (vector<2xi16>, vector<2xi16>, vector<16xf32>) -> vector<16xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.f32.32x32x4bf16' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: mfma_f32_32x32x4bf16Adaptor(operands: list[Value], attributes: OpAttributeMap) mfma_f32_32x32x4bf16Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.f32.32x32x4bf16' .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:function:: mfma_f32_32x32x4bf16_(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: mfma_f32_32x32x4bf16_1k(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Matrix fused multiply-add (MFMA) intrinsic. Computes ``D = A * B + C`` with matrix operands. The ``cbsz``, ``abid``, and ``blgp`` attributes control broadcast and block layout modes. Example: .. code:: mlir %r0 = mfma.f32.32x32x4bf16.1k %a0, %b0, %c0, 0, 0, none : (vector<4xi16>, vector<4xi16>, vector<32xf32>) -> vector<32xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.f32.32x32x4bf16.1k' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: mfma_f32_32x32x4bf16_1kAdaptor(operands: list[Value], attributes: OpAttributeMap) mfma_f32_32x32x4bf16_1kAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.f32.32x32x4bf16.1k' .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:function:: mfma_f32_32x32x4bf16_1k_(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: mfma_f32_32x32x4f16(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Matrix fused multiply-add (MFMA) intrinsic. Computes ``D = A * B + C`` with matrix operands. The ``cbsz``, ``abid``, and ``blgp`` attributes control broadcast and block layout modes. Example: .. code:: mlir %r0 = mfma.f32.32x32x4f16 %a0, %b0, %c0, 0, 0, none : (vector<4xf16>, vector<4xf16>, vector<32xf32>) -> vector<32xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.f32.32x32x4f16' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: mfma_f32_32x32x4f16Adaptor(operands: list[Value], attributes: OpAttributeMap) mfma_f32_32x32x4f16Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.f32.32x32x4f16' .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:function:: mfma_f32_32x32x4f16_(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: mfma_f32_32x32x8bf16_1k(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Matrix fused multiply-add (MFMA) intrinsic. Computes ``D = A * B + C`` with matrix operands. The ``cbsz``, ``abid``, and ``blgp`` attributes control broadcast and block layout modes. Example: .. code:: mlir %r0 = mfma.f32.32x32x8bf16.1k %a0, %b0, %c0, 0, 0, none : (vector<4xi16>, vector<4xi16>, vector<16xf32>) -> vector<16xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.f32.32x32x8bf16.1k' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: mfma_f32_32x32x8bf16_1kAdaptor(operands: list[Value], attributes: OpAttributeMap) mfma_f32_32x32x8bf16_1kAdaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.f32.32x32x8bf16.1k' .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:function:: mfma_f32_32x32x8bf16_1k_(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: mfma_f32_32x32x8f16(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Matrix fused multiply-add (MFMA) intrinsic. Computes ``D = A * B + C`` with matrix operands. The ``cbsz``, ``abid``, and ``blgp`` attributes control broadcast and block layout modes. Example: .. code:: mlir %r0 = mfma.f32.32x32x8f16 %a0, %b0, %c0, 0, 0, none : (vector<4xf16>, vector<4xf16>, vector<16xf32>) -> vector<16xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.f32.32x32x8f16' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: mfma_f32_32x32x8f16Adaptor(operands: list[Value], attributes: OpAttributeMap) mfma_f32_32x32x8f16Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.f32.32x32x8f16' .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:function:: mfma_f32_32x32x8f16_(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: mfma_f32_32x32x16_bf8_bf8(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Matrix fused multiply-add (MFMA) intrinsic. Computes ``D = A * B + C`` with matrix operands. The ``cbsz``, ``abid``, and ``blgp`` attributes control broadcast and block layout modes. Example: .. code:: mlir %r0 = mfma.f32.32x32x16.bf8.bf8 %a0, %b0, %c0, 0, 0, none : (i64, i64, vector<16xf32>) -> vector<16xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.f32.32x32x16.bf8.bf8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: mfma_f32_32x32x16_bf8_bf8Adaptor(operands: list[Value], attributes: OpAttributeMap) mfma_f32_32x32x16_bf8_bf8Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.f32.32x32x16.bf8.bf8' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:function:: mfma_f32_32x32x16_bf8_bf8_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: mfma_f32_32x32x16_bf8_fp8(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Matrix fused multiply-add (MFMA) intrinsic. Computes ``D = A * B + C`` with matrix operands. The ``cbsz``, ``abid``, and ``blgp`` attributes control broadcast and block layout modes. Example: .. code:: mlir %r0 = mfma.f32.32x32x16.bf8.fp8 %a0, %b0, %c0, 0, 0, none : (i64, i64, vector<16xf32>) -> vector<16xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.f32.32x32x16.bf8.fp8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: mfma_f32_32x32x16_bf8_fp8Adaptor(operands: list[Value], attributes: OpAttributeMap) mfma_f32_32x32x16_bf8_fp8Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.f32.32x32x16.bf8.fp8' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:function:: mfma_f32_32x32x16_bf8_fp8_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: mfma_f32_32x32x16_bf16(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Matrix fused multiply-add (MFMA) intrinsic. Computes ``D = A * B + C`` with matrix operands. The ``cbsz``, ``abid``, and ``blgp`` attributes control broadcast and block layout modes. Example: .. code:: mlir %r0 = mfma.f32.32x32x16.bf16 %a0, %b0, %c0, 0, 0, none : (vector<8xbf16>, vector<8xbf16>, vector<16xf32>) -> vector<16xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.f32.32x32x16.bf16' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: mfma_f32_32x32x16_bf16Adaptor(operands: list[Value], attributes: OpAttributeMap) mfma_f32_32x32x16_bf16Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.f32.32x32x16.bf16' .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:function:: mfma_f32_32x32x16_bf16_(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: mfma_f32_32x32x16_f16(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Matrix fused multiply-add (MFMA) intrinsic. Computes ``D = A * B + C`` with matrix operands. The ``cbsz``, ``abid``, and ``blgp`` attributes control broadcast and block layout modes. Example: .. code:: mlir %r0 = mfma.f32.32x32x16.f16 %a0, %b0, %c0, 0, 0, none : (vector<8xf16>, vector<8xf16>, vector<16xf32>) -> vector<16xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.f32.32x32x16.f16' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: mfma_f32_32x32x16_f16Adaptor(operands: list[Value], attributes: OpAttributeMap) mfma_f32_32x32x16_f16Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.f32.32x32x16.f16' .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:function:: mfma_f32_32x32x16_f16_(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: mfma_f32_32x32x16_fp8_bf8(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Matrix fused multiply-add (MFMA) intrinsic. Computes ``D = A * B + C`` with matrix operands. The ``cbsz``, ``abid``, and ``blgp`` attributes control broadcast and block layout modes. Example: .. code:: mlir %r0 = mfma.f32.32x32x16.fp8.bf8 %a0, %b0, %c0, 0, 0, none : (i64, i64, vector<16xf32>) -> vector<16xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.f32.32x32x16.fp8.bf8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: mfma_f32_32x32x16_fp8_bf8Adaptor(operands: list[Value], attributes: OpAttributeMap) mfma_f32_32x32x16_fp8_bf8Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.f32.32x32x16.fp8.bf8' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:function:: mfma_f32_32x32x16_fp8_bf8_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: mfma_f32_32x32x16_fp8_fp8(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Matrix fused multiply-add (MFMA) intrinsic. Computes ``D = A * B + C`` with matrix operands. The ``cbsz``, ``abid``, and ``blgp`` attributes control broadcast and block layout modes. Example: .. code:: mlir %r0 = mfma.f32.32x32x16.fp8.fp8 %a0, %b0, %c0, 0, 0, none : (i64, i64, vector<16xf32>) -> vector<16xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.f32.32x32x16.fp8.fp8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: mfma_f32_32x32x16_fp8_fp8Adaptor(operands: list[Value], attributes: OpAttributeMap) mfma_f32_32x32x16_fp8_fp8Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.f32.32x32x16.fp8.fp8' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:function:: mfma_f32_32x32x16_fp8_fp8_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: mfma_f64_4x4x4f64(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Double-precision matrix fused multiply-add (MFMA) intrinsic. On gfx94x, the ``blgp`` immarg is a NEG bitfield rather than a B-lane permutation. Example: .. code:: mlir %r0 = mfma.f64.4x4x4f64 %a0, %b0, %c0, 0, 0, neg_a|neg_b : (f64, f64, f64) -> f64 .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.f64.4x4x4f64' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: mfma_f64_4x4x4f64Adaptor(operands: list[Value], attributes: OpAttributeMap) mfma_f64_4x4x4f64Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.f64.4x4x4f64' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:function:: mfma_f64_4x4x4f64_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: mfma_f64_16x16x4f64(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Double-precision matrix fused multiply-add (MFMA) intrinsic. On gfx94x, the ``blgp`` immarg is a NEG bitfield rather than a B-lane permutation. Example: .. code:: mlir %r0 = mfma.f64.16x16x4f64 %a0, %b0, %c0, 0, 0, neg_a|neg_b : (f64, f64, vector<4xf64>) -> vector<4xf64> .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.f64.16x16x4f64' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: mfma_f64_16x16x4f64Adaptor(operands: list[Value], attributes: OpAttributeMap) mfma_f64_16x16x4f64Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.f64.16x16x4f64' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:function:: mfma_f64_16x16x4f64_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: mfma_i32_4x4x4i8(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Matrix fused multiply-add (MFMA) intrinsic. Computes ``D = A * B + C`` with matrix operands. The ``cbsz``, ``abid``, and ``blgp`` attributes control broadcast and block layout modes. Example: .. code:: mlir %r0 = mfma.i32.4x4x4i8 %a0, %b0, %c0, 0, 0, none : (i32, i32, vector<4xi32>) -> vector<4xi32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.i32.4x4x4i8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: mfma_i32_4x4x4i8Adaptor(operands: list[Value], attributes: OpAttributeMap) mfma_i32_4x4x4i8Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.i32.4x4x4i8' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:function:: mfma_i32_4x4x4i8_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: mfma_i32_16x16x4i8(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Matrix fused multiply-add (MFMA) intrinsic. Computes ``D = A * B + C`` with matrix operands. The ``cbsz``, ``abid``, and ``blgp`` attributes control broadcast and block layout modes. Example: .. code:: mlir %r0 = mfma.i32.16x16x4i8 %a0, %b0, %c0, 0, 0, none : (i32, i32, vector<16xi32>) -> vector<16xi32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.i32.16x16x4i8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: mfma_i32_16x16x4i8Adaptor(operands: list[Value], attributes: OpAttributeMap) mfma_i32_16x16x4i8Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.i32.16x16x4i8' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:function:: mfma_i32_16x16x4i8_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: mfma_i32_16x16x16i8(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Matrix fused multiply-add (MFMA) intrinsic. Computes ``D = A * B + C`` with matrix operands. The ``cbsz``, ``abid``, and ``blgp`` attributes control broadcast and block layout modes. Example: .. code:: mlir %r0 = mfma.i32.16x16x16i8 %a0, %b0, %c0, 0, 0, none : (i32, i32, vector<4xi32>) -> vector<4xi32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.i32.16x16x16i8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: mfma_i32_16x16x16i8Adaptor(operands: list[Value], attributes: OpAttributeMap) mfma_i32_16x16x16i8Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.i32.16x16x16i8' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:function:: mfma_i32_16x16x16i8_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: mfma_i32_16x16x32_i8(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Matrix fused multiply-add (MFMA) intrinsic. Computes ``D = A * B + C`` with matrix operands. The ``cbsz``, ``abid``, and ``blgp`` attributes control broadcast and block layout modes. Example: .. code:: mlir %r0 = mfma.i32.16x16x32.i8 %a0, %b0, %c0, 0, 0, none : (i64, i64, vector<4xi32>) -> vector<4xi32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.i32.16x16x32.i8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: mfma_i32_16x16x32_i8Adaptor(operands: list[Value], attributes: OpAttributeMap) mfma_i32_16x16x32_i8Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.i32.16x16x32.i8' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:function:: mfma_i32_16x16x32_i8_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: mfma_i32_16x16x64_i8(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Matrix fused multiply-add (MFMA) intrinsic. Computes ``D = A * B + C`` with matrix operands. The ``cbsz``, ``abid``, and ``blgp`` attributes control broadcast and block layout modes. Example: .. code:: mlir %r0 = mfma.i32.16x16x64.i8 %a0, %b0, %c0, 0, 0, none : (vector<4xi32>, vector<4xi32>, vector<4xi32>) -> vector<4xi32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.i32.16x16x64.i8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: mfma_i32_16x16x64_i8Adaptor(operands: list[Value], attributes: OpAttributeMap) mfma_i32_16x16x64_i8Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.i32.16x16x64.i8' .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:function:: mfma_i32_16x16x64_i8_(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: mfma_i32_32x32x4i8(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Matrix fused multiply-add (MFMA) intrinsic. Computes ``D = A * B + C`` with matrix operands. The ``cbsz``, ``abid``, and ``blgp`` attributes control broadcast and block layout modes. Example: .. code:: mlir %r0 = mfma.i32.32x32x4i8 %a0, %b0, %c0, 0, 0, none : (i32, i32, vector<32xi32>) -> vector<32xi32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.i32.32x32x4i8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: mfma_i32_32x32x4i8Adaptor(operands: list[Value], attributes: OpAttributeMap) mfma_i32_32x32x4i8Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.i32.32x32x4i8' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:function:: mfma_i32_32x32x4i8_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: mfma_i32_32x32x8i8(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Matrix fused multiply-add (MFMA) intrinsic. Computes ``D = A * B + C`` with matrix operands. The ``cbsz``, ``abid``, and ``blgp`` attributes control broadcast and block layout modes. Example: .. code:: mlir %r0 = mfma.i32.32x32x8i8 %a0, %b0, %c0, 0, 0, none : (i32, i32, vector<16xi32>) -> vector<16xi32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.i32.32x32x8i8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: mfma_i32_32x32x8i8Adaptor(operands: list[Value], attributes: OpAttributeMap) mfma_i32_32x32x8i8Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.i32.32x32x8i8' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:function:: mfma_i32_32x32x8i8_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: mfma_i32_32x32x16_i8(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Matrix fused multiply-add (MFMA) intrinsic. Computes ``D = A * B + C`` with matrix operands. The ``cbsz``, ``abid``, and ``blgp`` attributes control broadcast and block layout modes. Example: .. code:: mlir %r0 = mfma.i32.32x32x16.i8 %a0, %b0, %c0, 0, 0, none : (i64, i64, vector<16xi32>) -> vector<16xi32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.i32.32x32x16.i8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: mfma_i32_32x32x16_i8Adaptor(operands: list[Value], attributes: OpAttributeMap) mfma_i32_32x32x16_i8Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.i32.32x32x16.i8' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:function:: mfma_i32_32x32x16_i8_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: mfma_i32_32x32x32_i8(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Matrix fused multiply-add (MFMA) intrinsic. Computes ``D = A * B + C`` with matrix operands. The ``cbsz``, ``abid``, and ``blgp`` attributes control broadcast and block layout modes. Example: .. code:: mlir %r0 = mfma.i32.32x32x32.i8 %a0, %b0, %c0, 0, 0, none : (vector<4xi32>, vector<4xi32>, vector<16xi32>) -> vector<16xi32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.i32.32x32x32.i8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: mfma_i32_32x32x32_i8Adaptor(operands: list[Value], attributes: OpAttributeMap) mfma_i32_32x32x32_i8Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.i32.32x32x32.i8' .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:function:: mfma_i32_32x32x32_i8_(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], blgp: Union[Any, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: mfma_scale_f32_16x16x128_f8f6f4(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], cbsz: Union[Any, _ods_ir], blgp: Union[Any, _ods_ir], opselA: Union[int, _ods_ir], scaleA: _ods_ir[_ods_ir], opselB: Union[int, _ods_ir], scaleB: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Scaled matrix fused multiply-add (MFMA) intrinsic with per-operand scaling. The ``opselA``/``opselB`` and ``scaleA``/``scaleB`` arguments control the scaling of input operands. Example: .. code:: mlir // Scaled MFMA with fp8 * fp8 inputs. %r0 = rocdl.mfma.scale.f32.32x32x64.f8f6f4 %a, %a, %c, fp8_e4m3, fp8_e4m3, 0, %scaleA, 0, %scaleB : (vector<8xi32>, vector<8xi32>, vector<16xf32>, i32, i32) -> vector<16xf32> // Scaled MFMA with fp8 * bf8 inputs. %r1 = rocdl.mfma.scale.f32.32x32x64.f8f6f4 %a, %a, %c, fp8_e4m3, fp8_e5m2, 0, %scaleA, 0, %scaleB : (vector<8xi32>, vector<8xi32>, vector<16xf32>, i32, i32) -> vector<16xf32> // Scaled MFMA with fp8 * fp6 inputs (6xi32 operand B). %r2 = rocdl.mfma.scale.f32.32x32x64.f8f6f4 %a, %b6, %c, fp8_e4m3, fp6_e2m3, 0, %scaleA, 0, %scaleB : (vector<8xi32>, vector<6xi32>, vector<16xf32>, i32, i32) -> vector<16xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.scale.f32.16x16x128.f8f6f4' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: scaleA() -> _ods_ir[_ods_ir] .. py:method:: scaleB() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:method:: opselA() -> _ods_ir .. py:method:: opselB() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: mfma_scale_f32_16x16x128_f8f6f4Adaptor(operands: list[Value], attributes: OpAttributeMap) mfma_scale_f32_16x16x128_f8f6f4Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.scale.f32.16x16x128.f8f6f4' .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: scaleA() -> _ods_ir[_ods_ir] .. py:method:: scaleB() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:method:: opselA() -> _ods_ir .. py:method:: opselB() -> _ods_ir .. py:function:: mfma_scale_f32_16x16x128_f8f6f4_(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], cbsz: Union[Any, _ods_ir], blgp: Union[Any, _ods_ir], opsel_a: Union[int, _ods_ir], scale_a: _ods_ir[_ods_ir], opsel_b: Union[int, _ods_ir], scale_b: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: mfma_scale_f32_32x32x64_f8f6f4(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], cbsz: Union[Any, _ods_ir], blgp: Union[Any, _ods_ir], opselA: Union[int, _ods_ir], scaleA: _ods_ir[_ods_ir], opselB: Union[int, _ods_ir], scaleB: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Scaled matrix fused multiply-add (MFMA) intrinsic with per-operand scaling. The ``opselA``/``opselB`` and ``scaleA``/``scaleB`` arguments control the scaling of input operands. Example: .. code:: mlir // Scaled MFMA with fp8 * fp8 inputs. %r0 = rocdl.mfma.scale.f32.32x32x64.f8f6f4 %a, %a, %c, fp8_e4m3, fp8_e4m3, 0, %scaleA, 0, %scaleB : (vector<8xi32>, vector<8xi32>, vector<16xf32>, i32, i32) -> vector<16xf32> // Scaled MFMA with fp8 * bf8 inputs. %r1 = rocdl.mfma.scale.f32.32x32x64.f8f6f4 %a, %a, %c, fp8_e4m3, fp8_e5m2, 0, %scaleA, 0, %scaleB : (vector<8xi32>, vector<8xi32>, vector<16xf32>, i32, i32) -> vector<16xf32> // Scaled MFMA with fp8 * fp6 inputs (6xi32 operand B). %r2 = rocdl.mfma.scale.f32.32x32x64.f8f6f4 %a, %b6, %c, fp8_e4m3, fp6_e2m3, 0, %scaleA, 0, %scaleB : (vector<8xi32>, vector<6xi32>, vector<16xf32>, i32, i32) -> vector<16xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.scale.f32.32x32x64.f8f6f4' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: scaleA() -> _ods_ir[_ods_ir] .. py:method:: scaleB() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:method:: opselA() -> _ods_ir .. py:method:: opselB() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: mfma_scale_f32_32x32x64_f8f6f4Adaptor(operands: list[Value], attributes: OpAttributeMap) mfma_scale_f32_32x32x64_f8f6f4Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.mfma.scale.f32.32x32x64.f8f6f4' .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: scaleA() -> _ods_ir[_ods_ir] .. py:method:: scaleB() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: blgp() -> _ods_ir .. py:method:: opselA() -> _ods_ir .. py:method:: opselB() -> _ods_ir .. py:function:: mfma_scale_f32_32x32x64_f8f6f4_(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], cbsz: Union[Any, _ods_ir], blgp: Union[Any, _ods_ir], opsel_a: Union[int, _ods_ir], scale_a: _ods_ir[_ods_ir], opsel_b: Union[int, _ods_ir], scale_b: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: sdot2(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir, *, clamp: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Packed intra-lane dot-product with optional result clamping (``clamp``). Computes ``res = sum_i a[i]*b[i] + c``, where ``a`` and ``b`` hold packed 4/8/16-bit data (for ``dot2``,``dot4``,``dot8``). Example: .. code:: mlir %r = rocdl.sdot2 %a, %b, %c {clamp = true} : (vector<2xi16>, vector<2xi16>, i32) -> i32 .. py:attribute:: OPERATION_NAME :value: 'rocdl.sdot2' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir .. py:method:: clamp() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: sdot2Adaptor(operands: list[Value], attributes: OpAttributeMap) sdot2Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.sdot2' .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir .. py:method:: clamp() -> _ods_ir .. py:function:: sdot2_(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir, *, clamp: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: sdot4(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, *, clamp: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Packed intra-lane dot-product with optional result clamping (``clamp``). Computes ``res = sum_i a[i]*b[i] + c``, where ``a`` and ``b`` hold packed 4/8/16-bit data (for ``dot2``,``dot4``,``dot8``). Example: .. code:: mlir %r = rocdl.sdot4 %a, %b, %c {clamp = true} : (i32, i32, i32) -> i32 .. py:attribute:: OPERATION_NAME :value: 'rocdl.sdot4' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: clamp() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: sdot4Adaptor(operands: list[Value], attributes: OpAttributeMap) sdot4Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.sdot4' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: clamp() -> _ods_ir .. py:function:: sdot4_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, *, clamp: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: sdot8(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, *, clamp: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Packed intra-lane dot-product with optional result clamping (``clamp``). Computes ``res = sum_i a[i]*b[i] + c``, where ``a`` and ``b`` hold packed 4/8/16-bit data (for ``dot2``,``dot4``,``dot8``). Example: .. code:: mlir %r = rocdl.sdot8 %a, %b, %c {clamp = true} : (i32, i32, i32) -> i32 .. py:attribute:: OPERATION_NAME :value: 'rocdl.sdot8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: clamp() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: sdot8Adaptor(operands: list[Value], attributes: OpAttributeMap) sdot8Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.sdot8' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: clamp() -> _ods_ir .. py:function:: sdot8_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, *, clamp: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: smfmac_f32_16x16x32_bf16(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], index: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Sparse matrix fused multiply-accumulate (SMFMAC) intrinsic with 2:4 structured sparsity. The ``index`` operand provides the sparsity metadata, and ``cbsz``/``abid`` control broadcast modes. Example: .. code:: mlir // SMFMAC with f16 inputs. %r0 = rocdl.smfmac.f32.16x16x32.f16 %a0, %b0, %c0, %idx, 0, 0 : (vector<4xf16>, vector<8xf16>, vector<4xf32>, i32) -> vector<4xf32> // SMFMAC with bf16 inputs. %r1 = rocdl.smfmac.f32.16x16x32.bf16 %a1, %b1, %c0, %idx, 0, 0 : (vector<4xi16>, vector<8xi16>, vector<4xf32>, i32) -> vector<4xf32> // SMFMAC with i8 inputs and i32 accumulator. %r2 = rocdl.smfmac.i32.16x16x64.i8 %a2, %b2, %c2, %idx, 0, 0 : (vector<2xi32>, vector<4xi32>, vector<4xi32>, i32) -> vector<4xi32> // SMFMAC with fp8 inputs. %r3 = rocdl.smfmac.f32.16x16x64.fp8.fp8 %a2, %b2, %c0, %idx, 0, 0 : (vector<2xi32>, vector<4xi32>, vector<4xf32>, i32) -> vector<4xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.smfmac.f32.16x16x32.bf16' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: smfmac_f32_16x16x32_bf16Adaptor(operands: list[Value], attributes: OpAttributeMap) smfmac_f32_16x16x32_bf16Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.smfmac.f32.16x16x32.bf16' .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:function:: smfmac_f32_16x16x32_bf16_(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], index: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: smfmac_f32_16x16x32_f16(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], index: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Sparse matrix fused multiply-accumulate (SMFMAC) intrinsic with 2:4 structured sparsity. The ``index`` operand provides the sparsity metadata, and ``cbsz``/``abid`` control broadcast modes. Example: .. code:: mlir // SMFMAC with f16 inputs. %r0 = rocdl.smfmac.f32.16x16x32.f16 %a0, %b0, %c0, %idx, 0, 0 : (vector<4xf16>, vector<8xf16>, vector<4xf32>, i32) -> vector<4xf32> // SMFMAC with bf16 inputs. %r1 = rocdl.smfmac.f32.16x16x32.bf16 %a1, %b1, %c0, %idx, 0, 0 : (vector<4xi16>, vector<8xi16>, vector<4xf32>, i32) -> vector<4xf32> // SMFMAC with i8 inputs and i32 accumulator. %r2 = rocdl.smfmac.i32.16x16x64.i8 %a2, %b2, %c2, %idx, 0, 0 : (vector<2xi32>, vector<4xi32>, vector<4xi32>, i32) -> vector<4xi32> // SMFMAC with fp8 inputs. %r3 = rocdl.smfmac.f32.16x16x64.fp8.fp8 %a2, %b2, %c0, %idx, 0, 0 : (vector<2xi32>, vector<4xi32>, vector<4xf32>, i32) -> vector<4xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.smfmac.f32.16x16x32.f16' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: smfmac_f32_16x16x32_f16Adaptor(operands: list[Value], attributes: OpAttributeMap) smfmac_f32_16x16x32_f16Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.smfmac.f32.16x16x32.f16' .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:function:: smfmac_f32_16x16x32_f16_(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], index: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: smfmac_f32_16x16x64_bf8_bf8(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], index: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Sparse matrix fused multiply-accumulate (SMFMAC) intrinsic with 2:4 structured sparsity. The ``index`` operand provides the sparsity metadata, and ``cbsz``/``abid`` control broadcast modes. Example: .. code:: mlir // SMFMAC with f16 inputs. %r0 = rocdl.smfmac.f32.16x16x32.f16 %a0, %b0, %c0, %idx, 0, 0 : (vector<4xf16>, vector<8xf16>, vector<4xf32>, i32) -> vector<4xf32> // SMFMAC with bf16 inputs. %r1 = rocdl.smfmac.f32.16x16x32.bf16 %a1, %b1, %c0, %idx, 0, 0 : (vector<4xi16>, vector<8xi16>, vector<4xf32>, i32) -> vector<4xf32> // SMFMAC with i8 inputs and i32 accumulator. %r2 = rocdl.smfmac.i32.16x16x64.i8 %a2, %b2, %c2, %idx, 0, 0 : (vector<2xi32>, vector<4xi32>, vector<4xi32>, i32) -> vector<4xi32> // SMFMAC with fp8 inputs. %r3 = rocdl.smfmac.f32.16x16x64.fp8.fp8 %a2, %b2, %c0, %idx, 0, 0 : (vector<2xi32>, vector<4xi32>, vector<4xf32>, i32) -> vector<4xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.smfmac.f32.16x16x64.bf8.bf8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: smfmac_f32_16x16x64_bf8_bf8Adaptor(operands: list[Value], attributes: OpAttributeMap) smfmac_f32_16x16x64_bf8_bf8Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.smfmac.f32.16x16x64.bf8.bf8' .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:function:: smfmac_f32_16x16x64_bf8_bf8_(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], index: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: smfmac_f32_16x16x64_bf8_fp8(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], index: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Sparse matrix fused multiply-accumulate (SMFMAC) intrinsic with 2:4 structured sparsity. The ``index`` operand provides the sparsity metadata, and ``cbsz``/``abid`` control broadcast modes. Example: .. code:: mlir // SMFMAC with f16 inputs. %r0 = rocdl.smfmac.f32.16x16x32.f16 %a0, %b0, %c0, %idx, 0, 0 : (vector<4xf16>, vector<8xf16>, vector<4xf32>, i32) -> vector<4xf32> // SMFMAC with bf16 inputs. %r1 = rocdl.smfmac.f32.16x16x32.bf16 %a1, %b1, %c0, %idx, 0, 0 : (vector<4xi16>, vector<8xi16>, vector<4xf32>, i32) -> vector<4xf32> // SMFMAC with i8 inputs and i32 accumulator. %r2 = rocdl.smfmac.i32.16x16x64.i8 %a2, %b2, %c2, %idx, 0, 0 : (vector<2xi32>, vector<4xi32>, vector<4xi32>, i32) -> vector<4xi32> // SMFMAC with fp8 inputs. %r3 = rocdl.smfmac.f32.16x16x64.fp8.fp8 %a2, %b2, %c0, %idx, 0, 0 : (vector<2xi32>, vector<4xi32>, vector<4xf32>, i32) -> vector<4xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.smfmac.f32.16x16x64.bf8.fp8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: smfmac_f32_16x16x64_bf8_fp8Adaptor(operands: list[Value], attributes: OpAttributeMap) smfmac_f32_16x16x64_bf8_fp8Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.smfmac.f32.16x16x64.bf8.fp8' .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:function:: smfmac_f32_16x16x64_bf8_fp8_(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], index: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: smfmac_f32_16x16x64_bf16(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], index: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Sparse matrix fused multiply-accumulate (SMFMAC) intrinsic with 2:4 structured sparsity. The ``index`` operand provides the sparsity metadata, and ``cbsz``/``abid`` control broadcast modes. Example: .. code:: mlir // SMFMAC with f16 inputs. %r0 = rocdl.smfmac.f32.16x16x32.f16 %a0, %b0, %c0, %idx, 0, 0 : (vector<4xf16>, vector<8xf16>, vector<4xf32>, i32) -> vector<4xf32> // SMFMAC with bf16 inputs. %r1 = rocdl.smfmac.f32.16x16x32.bf16 %a1, %b1, %c0, %idx, 0, 0 : (vector<4xi16>, vector<8xi16>, vector<4xf32>, i32) -> vector<4xf32> // SMFMAC with i8 inputs and i32 accumulator. %r2 = rocdl.smfmac.i32.16x16x64.i8 %a2, %b2, %c2, %idx, 0, 0 : (vector<2xi32>, vector<4xi32>, vector<4xi32>, i32) -> vector<4xi32> // SMFMAC with fp8 inputs. %r3 = rocdl.smfmac.f32.16x16x64.fp8.fp8 %a2, %b2, %c0, %idx, 0, 0 : (vector<2xi32>, vector<4xi32>, vector<4xf32>, i32) -> vector<4xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.smfmac.f32.16x16x64.bf16' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: smfmac_f32_16x16x64_bf16Adaptor(operands: list[Value], attributes: OpAttributeMap) smfmac_f32_16x16x64_bf16Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.smfmac.f32.16x16x64.bf16' .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:function:: smfmac_f32_16x16x64_bf16_(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], index: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: smfmac_f32_16x16x64_f16(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], index: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Sparse matrix fused multiply-accumulate (SMFMAC) intrinsic with 2:4 structured sparsity. The ``index`` operand provides the sparsity metadata, and ``cbsz``/``abid`` control broadcast modes. Example: .. code:: mlir // SMFMAC with f16 inputs. %r0 = rocdl.smfmac.f32.16x16x32.f16 %a0, %b0, %c0, %idx, 0, 0 : (vector<4xf16>, vector<8xf16>, vector<4xf32>, i32) -> vector<4xf32> // SMFMAC with bf16 inputs. %r1 = rocdl.smfmac.f32.16x16x32.bf16 %a1, %b1, %c0, %idx, 0, 0 : (vector<4xi16>, vector<8xi16>, vector<4xf32>, i32) -> vector<4xf32> // SMFMAC with i8 inputs and i32 accumulator. %r2 = rocdl.smfmac.i32.16x16x64.i8 %a2, %b2, %c2, %idx, 0, 0 : (vector<2xi32>, vector<4xi32>, vector<4xi32>, i32) -> vector<4xi32> // SMFMAC with fp8 inputs. %r3 = rocdl.smfmac.f32.16x16x64.fp8.fp8 %a2, %b2, %c0, %idx, 0, 0 : (vector<2xi32>, vector<4xi32>, vector<4xf32>, i32) -> vector<4xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.smfmac.f32.16x16x64.f16' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: smfmac_f32_16x16x64_f16Adaptor(operands: list[Value], attributes: OpAttributeMap) smfmac_f32_16x16x64_f16Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.smfmac.f32.16x16x64.f16' .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:function:: smfmac_f32_16x16x64_f16_(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], index: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: smfmac_f32_16x16x64_fp8_bf8(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], index: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Sparse matrix fused multiply-accumulate (SMFMAC) intrinsic with 2:4 structured sparsity. The ``index`` operand provides the sparsity metadata, and ``cbsz``/``abid`` control broadcast modes. Example: .. code:: mlir // SMFMAC with f16 inputs. %r0 = rocdl.smfmac.f32.16x16x32.f16 %a0, %b0, %c0, %idx, 0, 0 : (vector<4xf16>, vector<8xf16>, vector<4xf32>, i32) -> vector<4xf32> // SMFMAC with bf16 inputs. %r1 = rocdl.smfmac.f32.16x16x32.bf16 %a1, %b1, %c0, %idx, 0, 0 : (vector<4xi16>, vector<8xi16>, vector<4xf32>, i32) -> vector<4xf32> // SMFMAC with i8 inputs and i32 accumulator. %r2 = rocdl.smfmac.i32.16x16x64.i8 %a2, %b2, %c2, %idx, 0, 0 : (vector<2xi32>, vector<4xi32>, vector<4xi32>, i32) -> vector<4xi32> // SMFMAC with fp8 inputs. %r3 = rocdl.smfmac.f32.16x16x64.fp8.fp8 %a2, %b2, %c0, %idx, 0, 0 : (vector<2xi32>, vector<4xi32>, vector<4xf32>, i32) -> vector<4xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.smfmac.f32.16x16x64.fp8.bf8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: smfmac_f32_16x16x64_fp8_bf8Adaptor(operands: list[Value], attributes: OpAttributeMap) smfmac_f32_16x16x64_fp8_bf8Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.smfmac.f32.16x16x64.fp8.bf8' .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:function:: smfmac_f32_16x16x64_fp8_bf8_(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], index: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: smfmac_f32_16x16x64_fp8_fp8(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], index: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Sparse matrix fused multiply-accumulate (SMFMAC) intrinsic with 2:4 structured sparsity. The ``index`` operand provides the sparsity metadata, and ``cbsz``/``abid`` control broadcast modes. Example: .. code:: mlir // SMFMAC with f16 inputs. %r0 = rocdl.smfmac.f32.16x16x32.f16 %a0, %b0, %c0, %idx, 0, 0 : (vector<4xf16>, vector<8xf16>, vector<4xf32>, i32) -> vector<4xf32> // SMFMAC with bf16 inputs. %r1 = rocdl.smfmac.f32.16x16x32.bf16 %a1, %b1, %c0, %idx, 0, 0 : (vector<4xi16>, vector<8xi16>, vector<4xf32>, i32) -> vector<4xf32> // SMFMAC with i8 inputs and i32 accumulator. %r2 = rocdl.smfmac.i32.16x16x64.i8 %a2, %b2, %c2, %idx, 0, 0 : (vector<2xi32>, vector<4xi32>, vector<4xi32>, i32) -> vector<4xi32> // SMFMAC with fp8 inputs. %r3 = rocdl.smfmac.f32.16x16x64.fp8.fp8 %a2, %b2, %c0, %idx, 0, 0 : (vector<2xi32>, vector<4xi32>, vector<4xf32>, i32) -> vector<4xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.smfmac.f32.16x16x64.fp8.fp8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: smfmac_f32_16x16x64_fp8_fp8Adaptor(operands: list[Value], attributes: OpAttributeMap) smfmac_f32_16x16x64_fp8_fp8Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.smfmac.f32.16x16x64.fp8.fp8' .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:function:: smfmac_f32_16x16x64_fp8_fp8_(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], index: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: smfmac_f32_16x16x128_bf8_bf8(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], index: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Sparse matrix fused multiply-accumulate (SMFMAC) intrinsic with 2:4 structured sparsity. The ``index`` operand provides the sparsity metadata, and ``cbsz``/``abid`` control broadcast modes. Example: .. code:: mlir // SMFMAC with f16 inputs. %r0 = rocdl.smfmac.f32.16x16x32.f16 %a0, %b0, %c0, %idx, 0, 0 : (vector<4xf16>, vector<8xf16>, vector<4xf32>, i32) -> vector<4xf32> // SMFMAC with bf16 inputs. %r1 = rocdl.smfmac.f32.16x16x32.bf16 %a1, %b1, %c0, %idx, 0, 0 : (vector<4xi16>, vector<8xi16>, vector<4xf32>, i32) -> vector<4xf32> // SMFMAC with i8 inputs and i32 accumulator. %r2 = rocdl.smfmac.i32.16x16x64.i8 %a2, %b2, %c2, %idx, 0, 0 : (vector<2xi32>, vector<4xi32>, vector<4xi32>, i32) -> vector<4xi32> // SMFMAC with fp8 inputs. %r3 = rocdl.smfmac.f32.16x16x64.fp8.fp8 %a2, %b2, %c0, %idx, 0, 0 : (vector<2xi32>, vector<4xi32>, vector<4xf32>, i32) -> vector<4xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.smfmac.f32.16x16x128.bf8.bf8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: smfmac_f32_16x16x128_bf8_bf8Adaptor(operands: list[Value], attributes: OpAttributeMap) smfmac_f32_16x16x128_bf8_bf8Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.smfmac.f32.16x16x128.bf8.bf8' .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:function:: smfmac_f32_16x16x128_bf8_bf8_(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], index: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: smfmac_f32_16x16x128_bf8_fp8(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], index: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Sparse matrix fused multiply-accumulate (SMFMAC) intrinsic with 2:4 structured sparsity. The ``index`` operand provides the sparsity metadata, and ``cbsz``/``abid`` control broadcast modes. Example: .. code:: mlir // SMFMAC with f16 inputs. %r0 = rocdl.smfmac.f32.16x16x32.f16 %a0, %b0, %c0, %idx, 0, 0 : (vector<4xf16>, vector<8xf16>, vector<4xf32>, i32) -> vector<4xf32> // SMFMAC with bf16 inputs. %r1 = rocdl.smfmac.f32.16x16x32.bf16 %a1, %b1, %c0, %idx, 0, 0 : (vector<4xi16>, vector<8xi16>, vector<4xf32>, i32) -> vector<4xf32> // SMFMAC with i8 inputs and i32 accumulator. %r2 = rocdl.smfmac.i32.16x16x64.i8 %a2, %b2, %c2, %idx, 0, 0 : (vector<2xi32>, vector<4xi32>, vector<4xi32>, i32) -> vector<4xi32> // SMFMAC with fp8 inputs. %r3 = rocdl.smfmac.f32.16x16x64.fp8.fp8 %a2, %b2, %c0, %idx, 0, 0 : (vector<2xi32>, vector<4xi32>, vector<4xf32>, i32) -> vector<4xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.smfmac.f32.16x16x128.bf8.fp8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: smfmac_f32_16x16x128_bf8_fp8Adaptor(operands: list[Value], attributes: OpAttributeMap) smfmac_f32_16x16x128_bf8_fp8Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.smfmac.f32.16x16x128.bf8.fp8' .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:function:: smfmac_f32_16x16x128_bf8_fp8_(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], index: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: smfmac_f32_16x16x128_fp8_bf8(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], index: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Sparse matrix fused multiply-accumulate (SMFMAC) intrinsic with 2:4 structured sparsity. The ``index`` operand provides the sparsity metadata, and ``cbsz``/``abid`` control broadcast modes. Example: .. code:: mlir // SMFMAC with f16 inputs. %r0 = rocdl.smfmac.f32.16x16x32.f16 %a0, %b0, %c0, %idx, 0, 0 : (vector<4xf16>, vector<8xf16>, vector<4xf32>, i32) -> vector<4xf32> // SMFMAC with bf16 inputs. %r1 = rocdl.smfmac.f32.16x16x32.bf16 %a1, %b1, %c0, %idx, 0, 0 : (vector<4xi16>, vector<8xi16>, vector<4xf32>, i32) -> vector<4xf32> // SMFMAC with i8 inputs and i32 accumulator. %r2 = rocdl.smfmac.i32.16x16x64.i8 %a2, %b2, %c2, %idx, 0, 0 : (vector<2xi32>, vector<4xi32>, vector<4xi32>, i32) -> vector<4xi32> // SMFMAC with fp8 inputs. %r3 = rocdl.smfmac.f32.16x16x64.fp8.fp8 %a2, %b2, %c0, %idx, 0, 0 : (vector<2xi32>, vector<4xi32>, vector<4xf32>, i32) -> vector<4xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.smfmac.f32.16x16x128.fp8.bf8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: smfmac_f32_16x16x128_fp8_bf8Adaptor(operands: list[Value], attributes: OpAttributeMap) smfmac_f32_16x16x128_fp8_bf8Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.smfmac.f32.16x16x128.fp8.bf8' .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:function:: smfmac_f32_16x16x128_fp8_bf8_(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], index: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: smfmac_f32_16x16x128_fp8_fp8(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], index: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Sparse matrix fused multiply-accumulate (SMFMAC) intrinsic with 2:4 structured sparsity. The ``index`` operand provides the sparsity metadata, and ``cbsz``/``abid`` control broadcast modes. Example: .. code:: mlir // SMFMAC with f16 inputs. %r0 = rocdl.smfmac.f32.16x16x32.f16 %a0, %b0, %c0, %idx, 0, 0 : (vector<4xf16>, vector<8xf16>, vector<4xf32>, i32) -> vector<4xf32> // SMFMAC with bf16 inputs. %r1 = rocdl.smfmac.f32.16x16x32.bf16 %a1, %b1, %c0, %idx, 0, 0 : (vector<4xi16>, vector<8xi16>, vector<4xf32>, i32) -> vector<4xf32> // SMFMAC with i8 inputs and i32 accumulator. %r2 = rocdl.smfmac.i32.16x16x64.i8 %a2, %b2, %c2, %idx, 0, 0 : (vector<2xi32>, vector<4xi32>, vector<4xi32>, i32) -> vector<4xi32> // SMFMAC with fp8 inputs. %r3 = rocdl.smfmac.f32.16x16x64.fp8.fp8 %a2, %b2, %c0, %idx, 0, 0 : (vector<2xi32>, vector<4xi32>, vector<4xf32>, i32) -> vector<4xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.smfmac.f32.16x16x128.fp8.fp8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: smfmac_f32_16x16x128_fp8_fp8Adaptor(operands: list[Value], attributes: OpAttributeMap) smfmac_f32_16x16x128_fp8_fp8Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.smfmac.f32.16x16x128.fp8.fp8' .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:function:: smfmac_f32_16x16x128_fp8_fp8_(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], index: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: smfmac_f32_32x32x16_bf16(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], index: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Sparse matrix fused multiply-accumulate (SMFMAC) intrinsic with 2:4 structured sparsity. The ``index`` operand provides the sparsity metadata, and ``cbsz``/``abid`` control broadcast modes. Example: .. code:: mlir // SMFMAC with f16 inputs. %r0 = rocdl.smfmac.f32.16x16x32.f16 %a0, %b0, %c0, %idx, 0, 0 : (vector<4xf16>, vector<8xf16>, vector<4xf32>, i32) -> vector<4xf32> // SMFMAC with bf16 inputs. %r1 = rocdl.smfmac.f32.16x16x32.bf16 %a1, %b1, %c0, %idx, 0, 0 : (vector<4xi16>, vector<8xi16>, vector<4xf32>, i32) -> vector<4xf32> // SMFMAC with i8 inputs and i32 accumulator. %r2 = rocdl.smfmac.i32.16x16x64.i8 %a2, %b2, %c2, %idx, 0, 0 : (vector<2xi32>, vector<4xi32>, vector<4xi32>, i32) -> vector<4xi32> // SMFMAC with fp8 inputs. %r3 = rocdl.smfmac.f32.16x16x64.fp8.fp8 %a2, %b2, %c0, %idx, 0, 0 : (vector<2xi32>, vector<4xi32>, vector<4xf32>, i32) -> vector<4xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.smfmac.f32.32x32x16.bf16' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: smfmac_f32_32x32x16_bf16Adaptor(operands: list[Value], attributes: OpAttributeMap) smfmac_f32_32x32x16_bf16Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.smfmac.f32.32x32x16.bf16' .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:function:: smfmac_f32_32x32x16_bf16_(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], index: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: smfmac_f32_32x32x16_f16(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], index: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Sparse matrix fused multiply-accumulate (SMFMAC) intrinsic with 2:4 structured sparsity. The ``index`` operand provides the sparsity metadata, and ``cbsz``/``abid`` control broadcast modes. Example: .. code:: mlir // SMFMAC with f16 inputs. %r0 = rocdl.smfmac.f32.16x16x32.f16 %a0, %b0, %c0, %idx, 0, 0 : (vector<4xf16>, vector<8xf16>, vector<4xf32>, i32) -> vector<4xf32> // SMFMAC with bf16 inputs. %r1 = rocdl.smfmac.f32.16x16x32.bf16 %a1, %b1, %c0, %idx, 0, 0 : (vector<4xi16>, vector<8xi16>, vector<4xf32>, i32) -> vector<4xf32> // SMFMAC with i8 inputs and i32 accumulator. %r2 = rocdl.smfmac.i32.16x16x64.i8 %a2, %b2, %c2, %idx, 0, 0 : (vector<2xi32>, vector<4xi32>, vector<4xi32>, i32) -> vector<4xi32> // SMFMAC with fp8 inputs. %r3 = rocdl.smfmac.f32.16x16x64.fp8.fp8 %a2, %b2, %c0, %idx, 0, 0 : (vector<2xi32>, vector<4xi32>, vector<4xf32>, i32) -> vector<4xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.smfmac.f32.32x32x16.f16' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: smfmac_f32_32x32x16_f16Adaptor(operands: list[Value], attributes: OpAttributeMap) smfmac_f32_32x32x16_f16Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.smfmac.f32.32x32x16.f16' .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:function:: smfmac_f32_32x32x16_f16_(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], index: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: smfmac_f32_32x32x32_bf8_bf8(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], index: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Sparse matrix fused multiply-accumulate (SMFMAC) intrinsic with 2:4 structured sparsity. The ``index`` operand provides the sparsity metadata, and ``cbsz``/``abid`` control broadcast modes. Example: .. code:: mlir // SMFMAC with f16 inputs. %r0 = rocdl.smfmac.f32.16x16x32.f16 %a0, %b0, %c0, %idx, 0, 0 : (vector<4xf16>, vector<8xf16>, vector<4xf32>, i32) -> vector<4xf32> // SMFMAC with bf16 inputs. %r1 = rocdl.smfmac.f32.16x16x32.bf16 %a1, %b1, %c0, %idx, 0, 0 : (vector<4xi16>, vector<8xi16>, vector<4xf32>, i32) -> vector<4xf32> // SMFMAC with i8 inputs and i32 accumulator. %r2 = rocdl.smfmac.i32.16x16x64.i8 %a2, %b2, %c2, %idx, 0, 0 : (vector<2xi32>, vector<4xi32>, vector<4xi32>, i32) -> vector<4xi32> // SMFMAC with fp8 inputs. %r3 = rocdl.smfmac.f32.16x16x64.fp8.fp8 %a2, %b2, %c0, %idx, 0, 0 : (vector<2xi32>, vector<4xi32>, vector<4xf32>, i32) -> vector<4xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.smfmac.f32.32x32x32.bf8.bf8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: smfmac_f32_32x32x32_bf8_bf8Adaptor(operands: list[Value], attributes: OpAttributeMap) smfmac_f32_32x32x32_bf8_bf8Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.smfmac.f32.32x32x32.bf8.bf8' .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:function:: smfmac_f32_32x32x32_bf8_bf8_(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], index: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: smfmac_f32_32x32x32_bf8_fp8(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], index: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Sparse matrix fused multiply-accumulate (SMFMAC) intrinsic with 2:4 structured sparsity. The ``index`` operand provides the sparsity metadata, and ``cbsz``/``abid`` control broadcast modes. Example: .. code:: mlir // SMFMAC with f16 inputs. %r0 = rocdl.smfmac.f32.16x16x32.f16 %a0, %b0, %c0, %idx, 0, 0 : (vector<4xf16>, vector<8xf16>, vector<4xf32>, i32) -> vector<4xf32> // SMFMAC with bf16 inputs. %r1 = rocdl.smfmac.f32.16x16x32.bf16 %a1, %b1, %c0, %idx, 0, 0 : (vector<4xi16>, vector<8xi16>, vector<4xf32>, i32) -> vector<4xf32> // SMFMAC with i8 inputs and i32 accumulator. %r2 = rocdl.smfmac.i32.16x16x64.i8 %a2, %b2, %c2, %idx, 0, 0 : (vector<2xi32>, vector<4xi32>, vector<4xi32>, i32) -> vector<4xi32> // SMFMAC with fp8 inputs. %r3 = rocdl.smfmac.f32.16x16x64.fp8.fp8 %a2, %b2, %c0, %idx, 0, 0 : (vector<2xi32>, vector<4xi32>, vector<4xf32>, i32) -> vector<4xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.smfmac.f32.32x32x32.bf8.fp8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: smfmac_f32_32x32x32_bf8_fp8Adaptor(operands: list[Value], attributes: OpAttributeMap) smfmac_f32_32x32x32_bf8_fp8Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.smfmac.f32.32x32x32.bf8.fp8' .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:function:: smfmac_f32_32x32x32_bf8_fp8_(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], index: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: smfmac_f32_32x32x32_bf16(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], index: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Sparse matrix fused multiply-accumulate (SMFMAC) intrinsic with 2:4 structured sparsity. The ``index`` operand provides the sparsity metadata, and ``cbsz``/``abid`` control broadcast modes. Example: .. code:: mlir // SMFMAC with f16 inputs. %r0 = rocdl.smfmac.f32.16x16x32.f16 %a0, %b0, %c0, %idx, 0, 0 : (vector<4xf16>, vector<8xf16>, vector<4xf32>, i32) -> vector<4xf32> // SMFMAC with bf16 inputs. %r1 = rocdl.smfmac.f32.16x16x32.bf16 %a1, %b1, %c0, %idx, 0, 0 : (vector<4xi16>, vector<8xi16>, vector<4xf32>, i32) -> vector<4xf32> // SMFMAC with i8 inputs and i32 accumulator. %r2 = rocdl.smfmac.i32.16x16x64.i8 %a2, %b2, %c2, %idx, 0, 0 : (vector<2xi32>, vector<4xi32>, vector<4xi32>, i32) -> vector<4xi32> // SMFMAC with fp8 inputs. %r3 = rocdl.smfmac.f32.16x16x64.fp8.fp8 %a2, %b2, %c0, %idx, 0, 0 : (vector<2xi32>, vector<4xi32>, vector<4xf32>, i32) -> vector<4xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.smfmac.f32.32x32x32.bf16' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: smfmac_f32_32x32x32_bf16Adaptor(operands: list[Value], attributes: OpAttributeMap) smfmac_f32_32x32x32_bf16Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.smfmac.f32.32x32x32.bf16' .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:function:: smfmac_f32_32x32x32_bf16_(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], index: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: smfmac_f32_32x32x32_f16(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], index: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Sparse matrix fused multiply-accumulate (SMFMAC) intrinsic with 2:4 structured sparsity. The ``index`` operand provides the sparsity metadata, and ``cbsz``/``abid`` control broadcast modes. Example: .. code:: mlir // SMFMAC with f16 inputs. %r0 = rocdl.smfmac.f32.16x16x32.f16 %a0, %b0, %c0, %idx, 0, 0 : (vector<4xf16>, vector<8xf16>, vector<4xf32>, i32) -> vector<4xf32> // SMFMAC with bf16 inputs. %r1 = rocdl.smfmac.f32.16x16x32.bf16 %a1, %b1, %c0, %idx, 0, 0 : (vector<4xi16>, vector<8xi16>, vector<4xf32>, i32) -> vector<4xf32> // SMFMAC with i8 inputs and i32 accumulator. %r2 = rocdl.smfmac.i32.16x16x64.i8 %a2, %b2, %c2, %idx, 0, 0 : (vector<2xi32>, vector<4xi32>, vector<4xi32>, i32) -> vector<4xi32> // SMFMAC with fp8 inputs. %r3 = rocdl.smfmac.f32.16x16x64.fp8.fp8 %a2, %b2, %c0, %idx, 0, 0 : (vector<2xi32>, vector<4xi32>, vector<4xf32>, i32) -> vector<4xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.smfmac.f32.32x32x32.f16' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: smfmac_f32_32x32x32_f16Adaptor(operands: list[Value], attributes: OpAttributeMap) smfmac_f32_32x32x32_f16Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.smfmac.f32.32x32x32.f16' .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:function:: smfmac_f32_32x32x32_f16_(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], index: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: smfmac_f32_32x32x32_fp8_bf8(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], index: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Sparse matrix fused multiply-accumulate (SMFMAC) intrinsic with 2:4 structured sparsity. The ``index`` operand provides the sparsity metadata, and ``cbsz``/``abid`` control broadcast modes. Example: .. code:: mlir // SMFMAC with f16 inputs. %r0 = rocdl.smfmac.f32.16x16x32.f16 %a0, %b0, %c0, %idx, 0, 0 : (vector<4xf16>, vector<8xf16>, vector<4xf32>, i32) -> vector<4xf32> // SMFMAC with bf16 inputs. %r1 = rocdl.smfmac.f32.16x16x32.bf16 %a1, %b1, %c0, %idx, 0, 0 : (vector<4xi16>, vector<8xi16>, vector<4xf32>, i32) -> vector<4xf32> // SMFMAC with i8 inputs and i32 accumulator. %r2 = rocdl.smfmac.i32.16x16x64.i8 %a2, %b2, %c2, %idx, 0, 0 : (vector<2xi32>, vector<4xi32>, vector<4xi32>, i32) -> vector<4xi32> // SMFMAC with fp8 inputs. %r3 = rocdl.smfmac.f32.16x16x64.fp8.fp8 %a2, %b2, %c0, %idx, 0, 0 : (vector<2xi32>, vector<4xi32>, vector<4xf32>, i32) -> vector<4xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.smfmac.f32.32x32x32.fp8.bf8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: smfmac_f32_32x32x32_fp8_bf8Adaptor(operands: list[Value], attributes: OpAttributeMap) smfmac_f32_32x32x32_fp8_bf8Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.smfmac.f32.32x32x32.fp8.bf8' .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:function:: smfmac_f32_32x32x32_fp8_bf8_(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], index: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: smfmac_f32_32x32x32_fp8_fp8(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], index: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Sparse matrix fused multiply-accumulate (SMFMAC) intrinsic with 2:4 structured sparsity. The ``index`` operand provides the sparsity metadata, and ``cbsz``/``abid`` control broadcast modes. Example: .. code:: mlir // SMFMAC with f16 inputs. %r0 = rocdl.smfmac.f32.16x16x32.f16 %a0, %b0, %c0, %idx, 0, 0 : (vector<4xf16>, vector<8xf16>, vector<4xf32>, i32) -> vector<4xf32> // SMFMAC with bf16 inputs. %r1 = rocdl.smfmac.f32.16x16x32.bf16 %a1, %b1, %c0, %idx, 0, 0 : (vector<4xi16>, vector<8xi16>, vector<4xf32>, i32) -> vector<4xf32> // SMFMAC with i8 inputs and i32 accumulator. %r2 = rocdl.smfmac.i32.16x16x64.i8 %a2, %b2, %c2, %idx, 0, 0 : (vector<2xi32>, vector<4xi32>, vector<4xi32>, i32) -> vector<4xi32> // SMFMAC with fp8 inputs. %r3 = rocdl.smfmac.f32.16x16x64.fp8.fp8 %a2, %b2, %c0, %idx, 0, 0 : (vector<2xi32>, vector<4xi32>, vector<4xf32>, i32) -> vector<4xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.smfmac.f32.32x32x32.fp8.fp8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: smfmac_f32_32x32x32_fp8_fp8Adaptor(operands: list[Value], attributes: OpAttributeMap) smfmac_f32_32x32x32_fp8_fp8Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.smfmac.f32.32x32x32.fp8.fp8' .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:function:: smfmac_f32_32x32x32_fp8_fp8_(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], index: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: smfmac_f32_32x32x64_bf8_bf8(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], index: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Sparse matrix fused multiply-accumulate (SMFMAC) intrinsic with 2:4 structured sparsity. The ``index`` operand provides the sparsity metadata, and ``cbsz``/``abid`` control broadcast modes. Example: .. code:: mlir // SMFMAC with f16 inputs. %r0 = rocdl.smfmac.f32.16x16x32.f16 %a0, %b0, %c0, %idx, 0, 0 : (vector<4xf16>, vector<8xf16>, vector<4xf32>, i32) -> vector<4xf32> // SMFMAC with bf16 inputs. %r1 = rocdl.smfmac.f32.16x16x32.bf16 %a1, %b1, %c0, %idx, 0, 0 : (vector<4xi16>, vector<8xi16>, vector<4xf32>, i32) -> vector<4xf32> // SMFMAC with i8 inputs and i32 accumulator. %r2 = rocdl.smfmac.i32.16x16x64.i8 %a2, %b2, %c2, %idx, 0, 0 : (vector<2xi32>, vector<4xi32>, vector<4xi32>, i32) -> vector<4xi32> // SMFMAC with fp8 inputs. %r3 = rocdl.smfmac.f32.16x16x64.fp8.fp8 %a2, %b2, %c0, %idx, 0, 0 : (vector<2xi32>, vector<4xi32>, vector<4xf32>, i32) -> vector<4xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.smfmac.f32.32x32x64.bf8.bf8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: smfmac_f32_32x32x64_bf8_bf8Adaptor(operands: list[Value], attributes: OpAttributeMap) smfmac_f32_32x32x64_bf8_bf8Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.smfmac.f32.32x32x64.bf8.bf8' .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:function:: smfmac_f32_32x32x64_bf8_bf8_(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], index: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: smfmac_f32_32x32x64_bf8_fp8(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], index: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Sparse matrix fused multiply-accumulate (SMFMAC) intrinsic with 2:4 structured sparsity. The ``index`` operand provides the sparsity metadata, and ``cbsz``/``abid`` control broadcast modes. Example: .. code:: mlir // SMFMAC with f16 inputs. %r0 = rocdl.smfmac.f32.16x16x32.f16 %a0, %b0, %c0, %idx, 0, 0 : (vector<4xf16>, vector<8xf16>, vector<4xf32>, i32) -> vector<4xf32> // SMFMAC with bf16 inputs. %r1 = rocdl.smfmac.f32.16x16x32.bf16 %a1, %b1, %c0, %idx, 0, 0 : (vector<4xi16>, vector<8xi16>, vector<4xf32>, i32) -> vector<4xf32> // SMFMAC with i8 inputs and i32 accumulator. %r2 = rocdl.smfmac.i32.16x16x64.i8 %a2, %b2, %c2, %idx, 0, 0 : (vector<2xi32>, vector<4xi32>, vector<4xi32>, i32) -> vector<4xi32> // SMFMAC with fp8 inputs. %r3 = rocdl.smfmac.f32.16x16x64.fp8.fp8 %a2, %b2, %c0, %idx, 0, 0 : (vector<2xi32>, vector<4xi32>, vector<4xf32>, i32) -> vector<4xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.smfmac.f32.32x32x64.bf8.fp8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: smfmac_f32_32x32x64_bf8_fp8Adaptor(operands: list[Value], attributes: OpAttributeMap) smfmac_f32_32x32x64_bf8_fp8Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.smfmac.f32.32x32x64.bf8.fp8' .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:function:: smfmac_f32_32x32x64_bf8_fp8_(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], index: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: smfmac_f32_32x32x64_fp8_bf8(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], index: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Sparse matrix fused multiply-accumulate (SMFMAC) intrinsic with 2:4 structured sparsity. The ``index`` operand provides the sparsity metadata, and ``cbsz``/``abid`` control broadcast modes. Example: .. code:: mlir // SMFMAC with f16 inputs. %r0 = rocdl.smfmac.f32.16x16x32.f16 %a0, %b0, %c0, %idx, 0, 0 : (vector<4xf16>, vector<8xf16>, vector<4xf32>, i32) -> vector<4xf32> // SMFMAC with bf16 inputs. %r1 = rocdl.smfmac.f32.16x16x32.bf16 %a1, %b1, %c0, %idx, 0, 0 : (vector<4xi16>, vector<8xi16>, vector<4xf32>, i32) -> vector<4xf32> // SMFMAC with i8 inputs and i32 accumulator. %r2 = rocdl.smfmac.i32.16x16x64.i8 %a2, %b2, %c2, %idx, 0, 0 : (vector<2xi32>, vector<4xi32>, vector<4xi32>, i32) -> vector<4xi32> // SMFMAC with fp8 inputs. %r3 = rocdl.smfmac.f32.16x16x64.fp8.fp8 %a2, %b2, %c0, %idx, 0, 0 : (vector<2xi32>, vector<4xi32>, vector<4xf32>, i32) -> vector<4xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.smfmac.f32.32x32x64.fp8.bf8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: smfmac_f32_32x32x64_fp8_bf8Adaptor(operands: list[Value], attributes: OpAttributeMap) smfmac_f32_32x32x64_fp8_bf8Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.smfmac.f32.32x32x64.fp8.bf8' .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:function:: smfmac_f32_32x32x64_fp8_bf8_(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], index: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: smfmac_f32_32x32x64_fp8_fp8(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], index: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Sparse matrix fused multiply-accumulate (SMFMAC) intrinsic with 2:4 structured sparsity. The ``index`` operand provides the sparsity metadata, and ``cbsz``/``abid`` control broadcast modes. Example: .. code:: mlir // SMFMAC with f16 inputs. %r0 = rocdl.smfmac.f32.16x16x32.f16 %a0, %b0, %c0, %idx, 0, 0 : (vector<4xf16>, vector<8xf16>, vector<4xf32>, i32) -> vector<4xf32> // SMFMAC with bf16 inputs. %r1 = rocdl.smfmac.f32.16x16x32.bf16 %a1, %b1, %c0, %idx, 0, 0 : (vector<4xi16>, vector<8xi16>, vector<4xf32>, i32) -> vector<4xf32> // SMFMAC with i8 inputs and i32 accumulator. %r2 = rocdl.smfmac.i32.16x16x64.i8 %a2, %b2, %c2, %idx, 0, 0 : (vector<2xi32>, vector<4xi32>, vector<4xi32>, i32) -> vector<4xi32> // SMFMAC with fp8 inputs. %r3 = rocdl.smfmac.f32.16x16x64.fp8.fp8 %a2, %b2, %c0, %idx, 0, 0 : (vector<2xi32>, vector<4xi32>, vector<4xf32>, i32) -> vector<4xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.smfmac.f32.32x32x64.fp8.fp8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: smfmac_f32_32x32x64_fp8_fp8Adaptor(operands: list[Value], attributes: OpAttributeMap) smfmac_f32_32x32x64_fp8_fp8Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.smfmac.f32.32x32x64.fp8.fp8' .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:function:: smfmac_f32_32x32x64_fp8_fp8_(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], index: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: smfmac_i32_16x16x64_i8(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], index: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Sparse matrix fused multiply-accumulate (SMFMAC) intrinsic with 2:4 structured sparsity. The ``index`` operand provides the sparsity metadata, and ``cbsz``/``abid`` control broadcast modes. Example: .. code:: mlir // SMFMAC with f16 inputs. %r0 = rocdl.smfmac.f32.16x16x32.f16 %a0, %b0, %c0, %idx, 0, 0 : (vector<4xf16>, vector<8xf16>, vector<4xf32>, i32) -> vector<4xf32> // SMFMAC with bf16 inputs. %r1 = rocdl.smfmac.f32.16x16x32.bf16 %a1, %b1, %c0, %idx, 0, 0 : (vector<4xi16>, vector<8xi16>, vector<4xf32>, i32) -> vector<4xf32> // SMFMAC with i8 inputs and i32 accumulator. %r2 = rocdl.smfmac.i32.16x16x64.i8 %a2, %b2, %c2, %idx, 0, 0 : (vector<2xi32>, vector<4xi32>, vector<4xi32>, i32) -> vector<4xi32> // SMFMAC with fp8 inputs. %r3 = rocdl.smfmac.f32.16x16x64.fp8.fp8 %a2, %b2, %c0, %idx, 0, 0 : (vector<2xi32>, vector<4xi32>, vector<4xf32>, i32) -> vector<4xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.smfmac.i32.16x16x64.i8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: smfmac_i32_16x16x64_i8Adaptor(operands: list[Value], attributes: OpAttributeMap) smfmac_i32_16x16x64_i8Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.smfmac.i32.16x16x64.i8' .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:function:: smfmac_i32_16x16x64_i8_(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], index: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: smfmac_i32_16x16x128_i8(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], index: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Sparse matrix fused multiply-accumulate (SMFMAC) intrinsic with 2:4 structured sparsity. The ``index`` operand provides the sparsity metadata, and ``cbsz``/``abid`` control broadcast modes. Example: .. code:: mlir // SMFMAC with f16 inputs. %r0 = rocdl.smfmac.f32.16x16x32.f16 %a0, %b0, %c0, %idx, 0, 0 : (vector<4xf16>, vector<8xf16>, vector<4xf32>, i32) -> vector<4xf32> // SMFMAC with bf16 inputs. %r1 = rocdl.smfmac.f32.16x16x32.bf16 %a1, %b1, %c0, %idx, 0, 0 : (vector<4xi16>, vector<8xi16>, vector<4xf32>, i32) -> vector<4xf32> // SMFMAC with i8 inputs and i32 accumulator. %r2 = rocdl.smfmac.i32.16x16x64.i8 %a2, %b2, %c2, %idx, 0, 0 : (vector<2xi32>, vector<4xi32>, vector<4xi32>, i32) -> vector<4xi32> // SMFMAC with fp8 inputs. %r3 = rocdl.smfmac.f32.16x16x64.fp8.fp8 %a2, %b2, %c0, %idx, 0, 0 : (vector<2xi32>, vector<4xi32>, vector<4xf32>, i32) -> vector<4xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.smfmac.i32.16x16x128.i8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: smfmac_i32_16x16x128_i8Adaptor(operands: list[Value], attributes: OpAttributeMap) smfmac_i32_16x16x128_i8Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.smfmac.i32.16x16x128.i8' .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:function:: smfmac_i32_16x16x128_i8_(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], index: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: smfmac_i32_32x32x32_i8(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], index: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Sparse matrix fused multiply-accumulate (SMFMAC) intrinsic with 2:4 structured sparsity. The ``index`` operand provides the sparsity metadata, and ``cbsz``/``abid`` control broadcast modes. Example: .. code:: mlir // SMFMAC with f16 inputs. %r0 = rocdl.smfmac.f32.16x16x32.f16 %a0, %b0, %c0, %idx, 0, 0 : (vector<4xf16>, vector<8xf16>, vector<4xf32>, i32) -> vector<4xf32> // SMFMAC with bf16 inputs. %r1 = rocdl.smfmac.f32.16x16x32.bf16 %a1, %b1, %c0, %idx, 0, 0 : (vector<4xi16>, vector<8xi16>, vector<4xf32>, i32) -> vector<4xf32> // SMFMAC with i8 inputs and i32 accumulator. %r2 = rocdl.smfmac.i32.16x16x64.i8 %a2, %b2, %c2, %idx, 0, 0 : (vector<2xi32>, vector<4xi32>, vector<4xi32>, i32) -> vector<4xi32> // SMFMAC with fp8 inputs. %r3 = rocdl.smfmac.f32.16x16x64.fp8.fp8 %a2, %b2, %c0, %idx, 0, 0 : (vector<2xi32>, vector<4xi32>, vector<4xf32>, i32) -> vector<4xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.smfmac.i32.32x32x32.i8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: smfmac_i32_32x32x32_i8Adaptor(operands: list[Value], attributes: OpAttributeMap) smfmac_i32_32x32x32_i8Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.smfmac.i32.32x32x32.i8' .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:function:: smfmac_i32_32x32x32_i8_(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], index: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: smfmac_i32_32x32x64_i8(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], index: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Sparse matrix fused multiply-accumulate (SMFMAC) intrinsic with 2:4 structured sparsity. The ``index`` operand provides the sparsity metadata, and ``cbsz``/``abid`` control broadcast modes. Example: .. code:: mlir // SMFMAC with f16 inputs. %r0 = rocdl.smfmac.f32.16x16x32.f16 %a0, %b0, %c0, %idx, 0, 0 : (vector<4xf16>, vector<8xf16>, vector<4xf32>, i32) -> vector<4xf32> // SMFMAC with bf16 inputs. %r1 = rocdl.smfmac.f32.16x16x32.bf16 %a1, %b1, %c0, %idx, 0, 0 : (vector<4xi16>, vector<8xi16>, vector<4xf32>, i32) -> vector<4xf32> // SMFMAC with i8 inputs and i32 accumulator. %r2 = rocdl.smfmac.i32.16x16x64.i8 %a2, %b2, %c2, %idx, 0, 0 : (vector<2xi32>, vector<4xi32>, vector<4xi32>, i32) -> vector<4xi32> // SMFMAC with fp8 inputs. %r3 = rocdl.smfmac.f32.16x16x64.fp8.fp8 %a2, %b2, %c0, %idx, 0, 0 : (vector<2xi32>, vector<4xi32>, vector<4xf32>, i32) -> vector<4xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.smfmac.i32.32x32x64.i8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: smfmac_i32_32x32x64_i8Adaptor(operands: list[Value], attributes: OpAttributeMap) smfmac_i32_32x32x64_i8Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.smfmac.i32.32x32x64.i8' .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: cbsz() -> _ods_ir .. py:method:: abid() -> _ods_ir .. py:function:: smfmac_i32_32x32x64_i8_(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], index: _ods_ir[_ods_ir], cbsz: Union[int, _ods_ir], abid: Union[int, _ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: sudot4(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], *, signA: Optional[Union[bool, _ods_ir]] = None, signB: Optional[Union[bool, _ods_ir]] = None, clamp: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Mixed-signedness packed dot-product with per-operand sign controls. Computes ``res = sum_i a[i]*b[i] + c``. Each lane of ``a`` is treated as signed when ``signA = true``; when ``signA = false``, the unsigned lane value is zero-extended into a wider signed integer. ``signB`` controls the same for ``b``. ``clamp`` controls result clamping. These ops correspond to RDNA's unified mixed-sign ``v_dot4_i32_iu8`` and ``v_dot8_i32_iu4`` instructions (gfx11+). Example: .. code:: mlir %r = rocdl.sudot4 %a, %b, %c {signA = true, signB = false, clamp = true} : (i32, i32, i32) -> i32 .. py:attribute:: OPERATION_NAME :value: 'rocdl.sudot4' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: signA() -> _ods_ir .. py:method:: signB() -> _ods_ir .. py:method:: clamp() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: sudot4Adaptor(operands: list[Value], attributes: OpAttributeMap) sudot4Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.sudot4' .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: signA() -> _ods_ir .. py:method:: signB() -> _ods_ir .. py:method:: clamp() -> _ods_ir .. py:function:: sudot4_(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], *, sign_a: Optional[Union[bool, _ods_ir]] = None, sign_b: Optional[Union[bool, _ods_ir]] = None, clamp: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: sudot8(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], *, signA: Optional[Union[bool, _ods_ir]] = None, signB: Optional[Union[bool, _ods_ir]] = None, clamp: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Mixed-signedness packed dot-product with per-operand sign controls. Computes ``res = sum_i a[i]*b[i] + c``. Each lane of ``a`` is treated as signed when ``signA = true``; when ``signA = false``, the unsigned lane value is zero-extended into a wider signed integer. ``signB`` controls the same for ``b``. ``clamp`` controls result clamping. These ops correspond to RDNA's unified mixed-sign ``v_dot4_i32_iu8`` and ``v_dot8_i32_iu4`` instructions (gfx11+). Example: .. code:: mlir %r = rocdl.sudot8 %a, %b, %c {signA = true, signB = false, clamp = true} : (i32, i32, i32) -> i32 .. py:attribute:: OPERATION_NAME :value: 'rocdl.sudot8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: signA() -> _ods_ir .. py:method:: signB() -> _ods_ir .. py:method:: clamp() -> _ods_ir .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: sudot8Adaptor(operands: list[Value], attributes: OpAttributeMap) sudot8Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.sudot8' .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: signA() -> _ods_ir .. py:method:: signB() -> _ods_ir .. py:method:: clamp() -> _ods_ir .. py:function:: sudot8_(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], *, sign_a: Optional[Union[bool, _ods_ir]] = None, sign_b: Optional[Union[bool, _ods_ir]] = None, clamp: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: swmmac_bf16_16x16x32_bf16(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], index: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.swmmac.bf16.16x16x32.bf16' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: swmmac_bf16_16x16x32_bf16Adaptor(operands: list[Value], attributes: OpAttributeMap) swmmac_bf16_16x16x32_bf16Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.swmmac.bf16.16x16x32.bf16' .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: index() -> _ods_ir[_ods_ir] .. py:function:: swmmac_bf16_16x16x32_bf16_(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], index: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: swmmac_bf16_16x16x64_bf16(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, index: _ods_ir[_ods_ir], *, signA: Optional[Union[bool, _ods_ir]] = None, signB: Optional[Union[bool, _ods_ir]] = None, reuseA: Optional[Union[bool, _ods_ir]] = None, reuseB: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.swmmac.bf16.16x16x64.bf16' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: signA() -> _ods_ir .. py:method:: signB() -> _ods_ir .. py:method:: reuseA() -> _ods_ir .. py:method:: reuseB() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: swmmac_bf16_16x16x64_bf16Adaptor(operands: list[Value], attributes: OpAttributeMap) swmmac_bf16_16x16x64_bf16Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.swmmac.bf16.16x16x64.bf16' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: signA() -> _ods_ir .. py:method:: signB() -> _ods_ir .. py:method:: reuseA() -> _ods_ir .. py:method:: reuseB() -> _ods_ir .. py:function:: swmmac_bf16_16x16x64_bf16_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, index: _ods_ir[_ods_ir], *, sign_a: Optional[Union[bool, _ods_ir]] = None, sign_b: Optional[Union[bool, _ods_ir]] = None, reuse_a: Optional[Union[bool, _ods_ir]] = None, reuse_b: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: swmmac_bf16f32_16x16x64_bf16(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, index: _ods_ir[_ods_ir], *, signA: Optional[Union[bool, _ods_ir]] = None, signB: Optional[Union[bool, _ods_ir]] = None, reuseA: Optional[Union[bool, _ods_ir]] = None, reuseB: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.swmmac.bf16f32.16x16x64.bf16' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: signA() -> _ods_ir .. py:method:: signB() -> _ods_ir .. py:method:: reuseA() -> _ods_ir .. py:method:: reuseB() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: swmmac_bf16f32_16x16x64_bf16Adaptor(operands: list[Value], attributes: OpAttributeMap) swmmac_bf16f32_16x16x64_bf16Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.swmmac.bf16f32.16x16x64.bf16' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: signA() -> _ods_ir .. py:method:: signB() -> _ods_ir .. py:method:: reuseA() -> _ods_ir .. py:method:: reuseB() -> _ods_ir .. py:function:: swmmac_bf16f32_16x16x64_bf16_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, index: _ods_ir[_ods_ir], *, sign_a: Optional[Union[bool, _ods_ir]] = None, sign_b: Optional[Union[bool, _ods_ir]] = None, reuse_a: Optional[Union[bool, _ods_ir]] = None, reuse_b: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: swmmac_f16_16x16x32_f16(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], index: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.swmmac.f16.16x16x32.f16' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: swmmac_f16_16x16x32_f16Adaptor(operands: list[Value], attributes: OpAttributeMap) swmmac_f16_16x16x32_f16Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.swmmac.f16.16x16x32.f16' .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: index() -> _ods_ir[_ods_ir] .. py:function:: swmmac_f16_16x16x32_f16_(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], index: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: swmmac_f16_16x16x64_f16(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, index: _ods_ir[_ods_ir], *, signA: Optional[Union[bool, _ods_ir]] = None, signB: Optional[Union[bool, _ods_ir]] = None, reuseA: Optional[Union[bool, _ods_ir]] = None, reuseB: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.swmmac.f16.16x16x64.f16' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: signA() -> _ods_ir .. py:method:: signB() -> _ods_ir .. py:method:: reuseA() -> _ods_ir .. py:method:: reuseB() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: swmmac_f16_16x16x64_f16Adaptor(operands: list[Value], attributes: OpAttributeMap) swmmac_f16_16x16x64_f16Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.swmmac.f16.16x16x64.f16' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: signA() -> _ods_ir .. py:method:: signB() -> _ods_ir .. py:method:: reuseA() -> _ods_ir .. py:method:: reuseB() -> _ods_ir .. py:function:: swmmac_f16_16x16x64_f16_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, index: _ods_ir[_ods_ir], *, sign_a: Optional[Union[bool, _ods_ir]] = None, sign_b: Optional[Union[bool, _ods_ir]] = None, reuse_a: Optional[Union[bool, _ods_ir]] = None, reuse_b: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: swmmac_f16_16x16x128_bf8_bf8(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, index: _ods_ir[_ods_ir], *, reuseA: Optional[Union[bool, _ods_ir]] = None, reuseB: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.swmmac.f16.16x16x128.bf8.bf8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: reuseA() -> _ods_ir .. py:method:: reuseB() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: swmmac_f16_16x16x128_bf8_bf8Adaptor(operands: list[Value], attributes: OpAttributeMap) swmmac_f16_16x16x128_bf8_bf8Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.swmmac.f16.16x16x128.bf8.bf8' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: reuseA() -> _ods_ir .. py:method:: reuseB() -> _ods_ir .. py:function:: swmmac_f16_16x16x128_bf8_bf8_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, index: _ods_ir[_ods_ir], *, reuse_a: Optional[Union[bool, _ods_ir]] = None, reuse_b: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: swmmac_f16_16x16x128_bf8_fp8(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, index: _ods_ir[_ods_ir], *, reuseA: Optional[Union[bool, _ods_ir]] = None, reuseB: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.swmmac.f16.16x16x128.bf8.fp8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: reuseA() -> _ods_ir .. py:method:: reuseB() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: swmmac_f16_16x16x128_bf8_fp8Adaptor(operands: list[Value], attributes: OpAttributeMap) swmmac_f16_16x16x128_bf8_fp8Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.swmmac.f16.16x16x128.bf8.fp8' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: reuseA() -> _ods_ir .. py:method:: reuseB() -> _ods_ir .. py:function:: swmmac_f16_16x16x128_bf8_fp8_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, index: _ods_ir[_ods_ir], *, reuse_a: Optional[Union[bool, _ods_ir]] = None, reuse_b: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: swmmac_f16_16x16x128_fp8_bf8(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, index: _ods_ir[_ods_ir], *, reuseA: Optional[Union[bool, _ods_ir]] = None, reuseB: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.swmmac.f16.16x16x128.fp8.bf8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: reuseA() -> _ods_ir .. py:method:: reuseB() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: swmmac_f16_16x16x128_fp8_bf8Adaptor(operands: list[Value], attributes: OpAttributeMap) swmmac_f16_16x16x128_fp8_bf8Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.swmmac.f16.16x16x128.fp8.bf8' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: reuseA() -> _ods_ir .. py:method:: reuseB() -> _ods_ir .. py:function:: swmmac_f16_16x16x128_fp8_bf8_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, index: _ods_ir[_ods_ir], *, reuse_a: Optional[Union[bool, _ods_ir]] = None, reuse_b: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: swmmac_f16_16x16x128_fp8_fp8(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, index: _ods_ir[_ods_ir], *, reuseA: Optional[Union[bool, _ods_ir]] = None, reuseB: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.swmmac.f16.16x16x128.fp8.fp8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: reuseA() -> _ods_ir .. py:method:: reuseB() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: swmmac_f16_16x16x128_fp8_fp8Adaptor(operands: list[Value], attributes: OpAttributeMap) swmmac_f16_16x16x128_fp8_fp8Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.swmmac.f16.16x16x128.fp8.fp8' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: reuseA() -> _ods_ir .. py:method:: reuseB() -> _ods_ir .. py:function:: swmmac_f16_16x16x128_fp8_fp8_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, index: _ods_ir[_ods_ir], *, reuse_a: Optional[Union[bool, _ods_ir]] = None, reuse_b: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: swmmac_f32_16x16x32_bf8_bf8(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, index: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.swmmac.f32.16x16x32.bf8.bf8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: res() -> _ods_ir .. py:class:: swmmac_f32_16x16x32_bf8_bf8Adaptor(operands: list[Value], attributes: OpAttributeMap) swmmac_f32_16x16x32_bf8_bf8Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.swmmac.f32.16x16x32.bf8.bf8' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: index() -> _ods_ir[_ods_ir] .. py:function:: swmmac_f32_16x16x32_bf8_bf8_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, index: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: swmmac_f32_16x16x32_bf8_fp8(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, index: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.swmmac.f32.16x16x32.bf8.fp8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: res() -> _ods_ir .. py:class:: swmmac_f32_16x16x32_bf8_fp8Adaptor(operands: list[Value], attributes: OpAttributeMap) swmmac_f32_16x16x32_bf8_fp8Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.swmmac.f32.16x16x32.bf8.fp8' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: index() -> _ods_ir[_ods_ir] .. py:function:: swmmac_f32_16x16x32_bf8_fp8_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, index: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: swmmac_f32_16x16x32_bf16(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], index: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.swmmac.f32.16x16x32.bf16' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: swmmac_f32_16x16x32_bf16Adaptor(operands: list[Value], attributes: OpAttributeMap) swmmac_f32_16x16x32_bf16Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.swmmac.f32.16x16x32.bf16' .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: index() -> _ods_ir[_ods_ir] .. py:function:: swmmac_f32_16x16x32_bf16_(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], index: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: swmmac_f32_16x16x32_f16(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], index: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.swmmac.f32.16x16x32.f16' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: res() -> _ods_ir[_ods_ir] .. py:class:: swmmac_f32_16x16x32_f16Adaptor(operands: list[Value], attributes: OpAttributeMap) swmmac_f32_16x16x32_f16Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.swmmac.f32.16x16x32.f16' .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir[_ods_ir] .. py:method:: index() -> _ods_ir[_ods_ir] .. py:function:: swmmac_f32_16x16x32_f16_(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir[_ods_ir], index: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir[_ods_ir] .. py:class:: swmmac_f32_16x16x32_fp8_bf8(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, index: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.swmmac.f32.16x16x32.fp8.bf8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: res() -> _ods_ir .. py:class:: swmmac_f32_16x16x32_fp8_bf8Adaptor(operands: list[Value], attributes: OpAttributeMap) swmmac_f32_16x16x32_fp8_bf8Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.swmmac.f32.16x16x32.fp8.bf8' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: index() -> _ods_ir[_ods_ir] .. py:function:: swmmac_f32_16x16x32_fp8_bf8_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, index: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: swmmac_f32_16x16x32_fp8_fp8(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, index: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.swmmac.f32.16x16x32.fp8.fp8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: res() -> _ods_ir .. py:class:: swmmac_f32_16x16x32_fp8_fp8Adaptor(operands: list[Value], attributes: OpAttributeMap) swmmac_f32_16x16x32_fp8_fp8Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.swmmac.f32.16x16x32.fp8.fp8' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: index() -> _ods_ir[_ods_ir] .. py:function:: swmmac_f32_16x16x32_fp8_fp8_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, index: _ods_ir[_ods_ir], *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: swmmac_f32_16x16x64_bf16(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, index: _ods_ir[_ods_ir], *, signA: Optional[Union[bool, _ods_ir]] = None, signB: Optional[Union[bool, _ods_ir]] = None, reuseA: Optional[Union[bool, _ods_ir]] = None, reuseB: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.swmmac.f32.16x16x64.bf16' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: signA() -> _ods_ir .. py:method:: signB() -> _ods_ir .. py:method:: reuseA() -> _ods_ir .. py:method:: reuseB() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: swmmac_f32_16x16x64_bf16Adaptor(operands: list[Value], attributes: OpAttributeMap) swmmac_f32_16x16x64_bf16Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.swmmac.f32.16x16x64.bf16' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: signA() -> _ods_ir .. py:method:: signB() -> _ods_ir .. py:method:: reuseA() -> _ods_ir .. py:method:: reuseB() -> _ods_ir .. py:function:: swmmac_f32_16x16x64_bf16_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, index: _ods_ir[_ods_ir], *, sign_a: Optional[Union[bool, _ods_ir]] = None, sign_b: Optional[Union[bool, _ods_ir]] = None, reuse_a: Optional[Union[bool, _ods_ir]] = None, reuse_b: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: swmmac_f32_16x16x64_f16(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, index: _ods_ir[_ods_ir], *, signA: Optional[Union[bool, _ods_ir]] = None, signB: Optional[Union[bool, _ods_ir]] = None, reuseA: Optional[Union[bool, _ods_ir]] = None, reuseB: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.swmmac.f32.16x16x64.f16' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: signA() -> _ods_ir .. py:method:: signB() -> _ods_ir .. py:method:: reuseA() -> _ods_ir .. py:method:: reuseB() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: swmmac_f32_16x16x64_f16Adaptor(operands: list[Value], attributes: OpAttributeMap) swmmac_f32_16x16x64_f16Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.swmmac.f32.16x16x64.f16' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: signA() -> _ods_ir .. py:method:: signB() -> _ods_ir .. py:method:: reuseA() -> _ods_ir .. py:method:: reuseB() -> _ods_ir .. py:function:: swmmac_f32_16x16x64_f16_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, index: _ods_ir[_ods_ir], *, sign_a: Optional[Union[bool, _ods_ir]] = None, sign_b: Optional[Union[bool, _ods_ir]] = None, reuse_a: Optional[Union[bool, _ods_ir]] = None, reuse_b: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: swmmac_f32_16x16x128_bf8_bf8(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, index: _ods_ir[_ods_ir], *, reuseA: Optional[Union[bool, _ods_ir]] = None, reuseB: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.swmmac.f32.16x16x128.bf8.bf8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: reuseA() -> _ods_ir .. py:method:: reuseB() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: swmmac_f32_16x16x128_bf8_bf8Adaptor(operands: list[Value], attributes: OpAttributeMap) swmmac_f32_16x16x128_bf8_bf8Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.swmmac.f32.16x16x128.bf8.bf8' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: reuseA() -> _ods_ir .. py:method:: reuseB() -> _ods_ir .. py:function:: swmmac_f32_16x16x128_bf8_bf8_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, index: _ods_ir[_ods_ir], *, reuse_a: Optional[Union[bool, _ods_ir]] = None, reuse_b: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: swmmac_f32_16x16x128_bf8_fp8(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, index: _ods_ir[_ods_ir], *, reuseA: Optional[Union[bool, _ods_ir]] = None, reuseB: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.swmmac.f32.16x16x128.bf8.fp8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: reuseA() -> _ods_ir .. py:method:: reuseB() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: swmmac_f32_16x16x128_bf8_fp8Adaptor(operands: list[Value], attributes: OpAttributeMap) swmmac_f32_16x16x128_bf8_fp8Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.swmmac.f32.16x16x128.bf8.fp8' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: reuseA() -> _ods_ir .. py:method:: reuseB() -> _ods_ir .. py:function:: swmmac_f32_16x16x128_bf8_fp8_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, index: _ods_ir[_ods_ir], *, reuse_a: Optional[Union[bool, _ods_ir]] = None, reuse_b: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: swmmac_f32_16x16x128_fp8_bf8(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, index: _ods_ir[_ods_ir], *, reuseA: Optional[Union[bool, _ods_ir]] = None, reuseB: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.swmmac.f32.16x16x128.fp8.bf8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: reuseA() -> _ods_ir .. py:method:: reuseB() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: swmmac_f32_16x16x128_fp8_bf8Adaptor(operands: list[Value], attributes: OpAttributeMap) swmmac_f32_16x16x128_fp8_bf8Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.swmmac.f32.16x16x128.fp8.bf8' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: reuseA() -> _ods_ir .. py:method:: reuseB() -> _ods_ir .. py:function:: swmmac_f32_16x16x128_fp8_bf8_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, index: _ods_ir[_ods_ir], *, reuse_a: Optional[Union[bool, _ods_ir]] = None, reuse_b: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: swmmac_f32_16x16x128_fp8_fp8(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, index: _ods_ir[_ods_ir], *, reuseA: Optional[Union[bool, _ods_ir]] = None, reuseB: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.swmmac.f32.16x16x128.fp8.fp8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: reuseA() -> _ods_ir .. py:method:: reuseB() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: swmmac_f32_16x16x128_fp8_fp8Adaptor(operands: list[Value], attributes: OpAttributeMap) swmmac_f32_16x16x128_fp8_fp8Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.swmmac.f32.16x16x128.fp8.fp8' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: reuseA() -> _ods_ir .. py:method:: reuseB() -> _ods_ir .. py:function:: swmmac_f32_16x16x128_fp8_fp8_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, index: _ods_ir[_ods_ir], *, reuse_a: Optional[Union[bool, _ods_ir]] = None, reuse_b: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: swmmac_i32_16x16x32_iu4(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, index: _ods_ir[_ods_ir], *, signA: Optional[Union[bool, _ods_ir]] = None, signB: Optional[Union[bool, _ods_ir]] = None, clamp: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.swmmac.i32.16x16x32.iu4' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: signA() -> _ods_ir .. py:method:: signB() -> _ods_ir .. py:method:: clamp() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: swmmac_i32_16x16x32_iu4Adaptor(operands: list[Value], attributes: OpAttributeMap) swmmac_i32_16x16x32_iu4Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.swmmac.i32.16x16x32.iu4' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: signA() -> _ods_ir .. py:method:: signB() -> _ods_ir .. py:method:: clamp() -> _ods_ir .. py:function:: swmmac_i32_16x16x32_iu4_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, index: _ods_ir[_ods_ir], *, sign_a: Optional[Union[bool, _ods_ir]] = None, sign_b: Optional[Union[bool, _ods_ir]] = None, clamp: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: swmmac_i32_16x16x32_iu8(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, index: _ods_ir[_ods_ir], *, signA: Optional[Union[bool, _ods_ir]] = None, signB: Optional[Union[bool, _ods_ir]] = None, clamp: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.swmmac.i32.16x16x32.iu8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: signA() -> _ods_ir .. py:method:: signB() -> _ods_ir .. py:method:: clamp() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: swmmac_i32_16x16x32_iu8Adaptor(operands: list[Value], attributes: OpAttributeMap) swmmac_i32_16x16x32_iu8Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.swmmac.i32.16x16x32.iu8' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: signA() -> _ods_ir .. py:method:: signB() -> _ods_ir .. py:method:: clamp() -> _ods_ir .. py:function:: swmmac_i32_16x16x32_iu8_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, index: _ods_ir[_ods_ir], *, sign_a: Optional[Union[bool, _ods_ir]] = None, sign_b: Optional[Union[bool, _ods_ir]] = None, clamp: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: swmmac_i32_16x16x64_iu4(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, index: _ods_ir[_ods_ir], *, signA: Optional[Union[bool, _ods_ir]] = None, signB: Optional[Union[bool, _ods_ir]] = None, clamp: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.swmmac.i32.16x16x64.iu4' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: signA() -> _ods_ir .. py:method:: signB() -> _ods_ir .. py:method:: clamp() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: swmmac_i32_16x16x64_iu4Adaptor(operands: list[Value], attributes: OpAttributeMap) swmmac_i32_16x16x64_iu4Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.swmmac.i32.16x16x64.iu4' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: signA() -> _ods_ir .. py:method:: signB() -> _ods_ir .. py:method:: clamp() -> _ods_ir .. py:function:: swmmac_i32_16x16x64_iu4_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, index: _ods_ir[_ods_ir], *, sign_a: Optional[Union[bool, _ods_ir]] = None, sign_b: Optional[Union[bool, _ods_ir]] = None, clamp: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: swmmac_i32_16x16x128_iu8(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, index: _ods_ir[_ods_ir], *, signA: Optional[Union[bool, _ods_ir]] = None, signB: Optional[Union[bool, _ods_ir]] = None, reuseA: Optional[Union[bool, _ods_ir]] = None, reuseB: Optional[Union[bool, _ods_ir]] = None, clamp: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.swmmac.i32.16x16x128.iu8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: signA() -> _ods_ir .. py:method:: signB() -> _ods_ir .. py:method:: reuseA() -> _ods_ir .. py:method:: reuseB() -> _ods_ir .. py:method:: clamp() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: swmmac_i32_16x16x128_iu8Adaptor(operands: list[Value], attributes: OpAttributeMap) swmmac_i32_16x16x128_iu8Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.swmmac.i32.16x16x128.iu8' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: index() -> _ods_ir[_ods_ir] .. py:method:: signA() -> _ods_ir .. py:method:: signB() -> _ods_ir .. py:method:: reuseA() -> _ods_ir .. py:method:: reuseB() -> _ods_ir .. py:method:: clamp() -> _ods_ir .. py:function:: swmmac_i32_16x16x128_iu8_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, index: _ods_ir[_ods_ir], *, sign_a: Optional[Union[bool, _ods_ir]] = None, sign_b: Optional[Union[bool, _ods_ir]] = None, reuse_a: Optional[Union[bool, _ods_ir]] = None, reuse_b: Optional[Union[bool, _ods_ir]] = None, clamp: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: udot2(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir, *, clamp: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Packed intra-lane dot-product with optional result clamping (``clamp``). Computes ``res = sum_i a[i]*b[i] + c``, where ``a`` and ``b`` hold packed 4/8/16-bit data (for ``dot2``,``dot4``,``dot8``). Example: .. code:: mlir %r = rocdl.udot2 %a, %b, %c {clamp = true} : (vector<2xi16>, vector<2xi16>, i32) -> i32 .. py:attribute:: OPERATION_NAME :value: 'rocdl.udot2' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir .. py:method:: clamp() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: udot2Adaptor(operands: list[Value], attributes: OpAttributeMap) udot2Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.udot2' .. py:method:: a() -> _ods_ir[_ods_ir] .. py:method:: b() -> _ods_ir[_ods_ir] .. py:method:: c() -> _ods_ir .. py:method:: clamp() -> _ods_ir .. py:function:: udot2_(res: _ods_ir, a: _ods_ir[_ods_ir], b: _ods_ir[_ods_ir], c: _ods_ir, *, clamp: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: udot4(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, *, clamp: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Packed intra-lane dot-product with optional result clamping (``clamp``). Computes ``res = sum_i a[i]*b[i] + c``, where ``a`` and ``b`` hold packed 4/8/16-bit data (for ``dot2``,``dot4``,``dot8``). Example: .. code:: mlir %r = rocdl.udot4 %a, %b, %c {clamp = true} : (i32, i32, i32) -> i32 .. py:attribute:: OPERATION_NAME :value: 'rocdl.udot4' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: clamp() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: udot4Adaptor(operands: list[Value], attributes: OpAttributeMap) udot4Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.udot4' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: clamp() -> _ods_ir .. py:function:: udot4_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, *, clamp: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: udot8(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, *, clamp: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Packed intra-lane dot-product with optional result clamping (``clamp``). Computes ``res = sum_i a[i]*b[i] + c``, where ``a`` and ``b`` hold packed 4/8/16-bit data (for ``dot2``,``dot4``,``dot8``). Example: .. code:: mlir %r = rocdl.udot8 %a, %b, %c {clamp = true} : (i32, i32, i32) -> i32 .. py:attribute:: OPERATION_NAME :value: 'rocdl.udot8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: clamp() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: udot8Adaptor(operands: list[Value], attributes: OpAttributeMap) udot8Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.udot8' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: clamp() -> _ods_ir .. py:function:: udot8_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, *, clamp: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: wmma_bf16_16x16x16_bf16(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, *, opsel: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Wave Matrix Multiply-Accumulate (WMMA) with output operand selection. Example: .. code:: mlir // WMMA f16 with opsel control. %r = rocdl.wmma.f16.16x16x16.f16 %a, %b, %c : (vector<16xf16>, vector<16xf16>, vector<16xf16>) -> vector<16xf16> .. py:attribute:: OPERATION_NAME :value: 'rocdl.wmma.bf16.16x16x16.bf16' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: opsel() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: wmma_bf16_16x16x16_bf16Adaptor(operands: list[Value], attributes: OpAttributeMap) wmma_bf16_16x16x16_bf16Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.wmma.bf16.16x16x16.bf16' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: opsel() -> _ods_ir .. py:function:: wmma_bf16_16x16x16_bf16_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, *, opsel: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: wmma_bf16_16x16x32_bf16(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, *, modC: Optional[Union[Any, _ods_ir]] = None, reuseA: Optional[Union[bool, _ods_ir]] = None, reuseB: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Wave Matrix Multiply-Accumulate (WMMA) with modC and reuse controls. Example: .. code:: mlir // WMMA f32 with fp8 inputs and modC/reuse controls. %r = rocdl.wmma.f32.16x16x64.fp8_fp8 %a, %b, %c, modC = none : (vector<16xi32>, vector<16xi32>, vector<8xf32>) -> vector<8xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.wmma.bf16.16x16x32.bf16' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: modC() -> _ods_ir .. py:method:: reuseA() -> _ods_ir .. py:method:: reuseB() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: wmma_bf16_16x16x32_bf16Adaptor(operands: list[Value], attributes: OpAttributeMap) wmma_bf16_16x16x32_bf16Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.wmma.bf16.16x16x32.bf16' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: modC() -> _ods_ir .. py:method:: reuseA() -> _ods_ir .. py:method:: reuseB() -> _ods_ir .. py:function:: wmma_bf16_16x16x32_bf16_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, *, mod_c: Optional[Union[Any, _ods_ir]] = None, reuse_a: Optional[Union[bool, _ods_ir]] = None, reuse_b: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: wmma_bf16f32_16x16x32_bf16(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, *, modC: Optional[Union[Any, _ods_ir]] = None, reuseA: Optional[Union[bool, _ods_ir]] = None, reuseB: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Wave Matrix Multiply-Accumulate (WMMA) with different C and D types. Example: .. code:: mlir // WMMA bf16 output from f32 accumulator with bf16 inputs. %r = rocdl.wmma.bf16f32.16x16x32.bf16 %a, %b, %c, modC = none : (vector<16xbf16>, vector<16xbf16>, vector<8xf32>) -> vector<16xbf16> .. py:attribute:: OPERATION_NAME :value: 'rocdl.wmma.bf16f32.16x16x32.bf16' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: modC() -> _ods_ir .. py:method:: reuseA() -> _ods_ir .. py:method:: reuseB() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: wmma_bf16f32_16x16x32_bf16Adaptor(operands: list[Value], attributes: OpAttributeMap) wmma_bf16f32_16x16x32_bf16Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.wmma.bf16f32.16x16x32.bf16' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: modC() -> _ods_ir .. py:method:: reuseA() -> _ods_ir .. py:method:: reuseB() -> _ods_ir .. py:function:: wmma_bf16f32_16x16x32_bf16_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, *, mod_c: Optional[Union[Any, _ods_ir]] = None, reuse_a: Optional[Union[bool, _ods_ir]] = None, reuse_b: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: wmma_f16_16x16x16_f16(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, *, opsel: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Wave Matrix Multiply-Accumulate (WMMA) with output operand selection. Example: .. code:: mlir // WMMA f16 with opsel control. %r = rocdl.wmma.f16.16x16x16.f16 %a, %b, %c : (vector<16xf16>, vector<16xf16>, vector<16xf16>) -> vector<16xf16> .. py:attribute:: OPERATION_NAME :value: 'rocdl.wmma.f16.16x16x16.f16' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: opsel() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: wmma_f16_16x16x16_f16Adaptor(operands: list[Value], attributes: OpAttributeMap) wmma_f16_16x16x16_f16Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.wmma.f16.16x16x16.f16' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: opsel() -> _ods_ir .. py:function:: wmma_f16_16x16x16_f16_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, *, opsel: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: wmma_f16_16x16x32_f16(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, *, modC: Optional[Union[Any, _ods_ir]] = None, reuseA: Optional[Union[bool, _ods_ir]] = None, reuseB: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Wave Matrix Multiply-Accumulate (WMMA) with modC and reuse controls. Example: .. code:: mlir // WMMA f32 with fp8 inputs and modC/reuse controls. %r = rocdl.wmma.f32.16x16x64.fp8_fp8 %a, %b, %c, modC = none : (vector<16xi32>, vector<16xi32>, vector<8xf32>) -> vector<8xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.wmma.f16.16x16x32.f16' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: modC() -> _ods_ir .. py:method:: reuseA() -> _ods_ir .. py:method:: reuseB() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: wmma_f16_16x16x32_f16Adaptor(operands: list[Value], attributes: OpAttributeMap) wmma_f16_16x16x32_f16Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.wmma.f16.16x16x32.f16' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: modC() -> _ods_ir .. py:method:: reuseA() -> _ods_ir .. py:method:: reuseB() -> _ods_ir .. py:function:: wmma_f16_16x16x32_f16_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, *, mod_c: Optional[Union[Any, _ods_ir]] = None, reuse_a: Optional[Union[bool, _ods_ir]] = None, reuse_b: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: wmma_f16_16x16x64_bf8_bf8(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, *, modC: Optional[Union[Any, _ods_ir]] = None, reuseA: Optional[Union[bool, _ods_ir]] = None, reuseB: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Wave Matrix Multiply-Accumulate (WMMA) with modC and reuse controls. Example: .. code:: mlir // WMMA f32 with fp8 inputs and modC/reuse controls. %r = rocdl.wmma.f32.16x16x64.fp8_fp8 %a, %b, %c, modC = none : (vector<16xi32>, vector<16xi32>, vector<8xf32>) -> vector<8xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.wmma.f16.16x16x64.bf8_bf8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: modC() -> _ods_ir .. py:method:: reuseA() -> _ods_ir .. py:method:: reuseB() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: wmma_f16_16x16x64_bf8_bf8Adaptor(operands: list[Value], attributes: OpAttributeMap) wmma_f16_16x16x64_bf8_bf8Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.wmma.f16.16x16x64.bf8_bf8' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: modC() -> _ods_ir .. py:method:: reuseA() -> _ods_ir .. py:method:: reuseB() -> _ods_ir .. py:function:: wmma_f16_16x16x64_bf8_bf8_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, *, mod_c: Optional[Union[Any, _ods_ir]] = None, reuse_a: Optional[Union[bool, _ods_ir]] = None, reuse_b: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: wmma_f16_16x16x64_bf8_fp8(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, *, modC: Optional[Union[Any, _ods_ir]] = None, reuseA: Optional[Union[bool, _ods_ir]] = None, reuseB: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Wave Matrix Multiply-Accumulate (WMMA) with modC and reuse controls. Example: .. code:: mlir // WMMA f32 with fp8 inputs and modC/reuse controls. %r = rocdl.wmma.f32.16x16x64.fp8_fp8 %a, %b, %c, modC = none : (vector<16xi32>, vector<16xi32>, vector<8xf32>) -> vector<8xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.wmma.f16.16x16x64.bf8_fp8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: modC() -> _ods_ir .. py:method:: reuseA() -> _ods_ir .. py:method:: reuseB() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: wmma_f16_16x16x64_bf8_fp8Adaptor(operands: list[Value], attributes: OpAttributeMap) wmma_f16_16x16x64_bf8_fp8Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.wmma.f16.16x16x64.bf8_fp8' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: modC() -> _ods_ir .. py:method:: reuseA() -> _ods_ir .. py:method:: reuseB() -> _ods_ir .. py:function:: wmma_f16_16x16x64_bf8_fp8_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, *, mod_c: Optional[Union[Any, _ods_ir]] = None, reuse_a: Optional[Union[bool, _ods_ir]] = None, reuse_b: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: wmma_f16_16x16x64_fp8_bf8(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, *, modC: Optional[Union[Any, _ods_ir]] = None, reuseA: Optional[Union[bool, _ods_ir]] = None, reuseB: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Wave Matrix Multiply-Accumulate (WMMA) with modC and reuse controls. Example: .. code:: mlir // WMMA f32 with fp8 inputs and modC/reuse controls. %r = rocdl.wmma.f32.16x16x64.fp8_fp8 %a, %b, %c, modC = none : (vector<16xi32>, vector<16xi32>, vector<8xf32>) -> vector<8xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.wmma.f16.16x16x64.fp8_bf8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: modC() -> _ods_ir .. py:method:: reuseA() -> _ods_ir .. py:method:: reuseB() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: wmma_f16_16x16x64_fp8_bf8Adaptor(operands: list[Value], attributes: OpAttributeMap) wmma_f16_16x16x64_fp8_bf8Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.wmma.f16.16x16x64.fp8_bf8' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: modC() -> _ods_ir .. py:method:: reuseA() -> _ods_ir .. py:method:: reuseB() -> _ods_ir .. py:function:: wmma_f16_16x16x64_fp8_bf8_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, *, mod_c: Optional[Union[Any, _ods_ir]] = None, reuse_a: Optional[Union[bool, _ods_ir]] = None, reuse_b: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: wmma_f16_16x16x64_fp8_fp8(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, *, modC: Optional[Union[Any, _ods_ir]] = None, reuseA: Optional[Union[bool, _ods_ir]] = None, reuseB: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Wave Matrix Multiply-Accumulate (WMMA) with modC and reuse controls. Example: .. code:: mlir // WMMA f32 with fp8 inputs and modC/reuse controls. %r = rocdl.wmma.f32.16x16x64.fp8_fp8 %a, %b, %c, modC = none : (vector<16xi32>, vector<16xi32>, vector<8xf32>) -> vector<8xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.wmma.f16.16x16x64.fp8_fp8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: modC() -> _ods_ir .. py:method:: reuseA() -> _ods_ir .. py:method:: reuseB() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: wmma_f16_16x16x64_fp8_fp8Adaptor(operands: list[Value], attributes: OpAttributeMap) wmma_f16_16x16x64_fp8_fp8Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.wmma.f16.16x16x64.fp8_fp8' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: modC() -> _ods_ir .. py:method:: reuseA() -> _ods_ir .. py:method:: reuseB() -> _ods_ir .. py:function:: wmma_f16_16x16x64_fp8_fp8_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, *, mod_c: Optional[Union[Any, _ods_ir]] = None, reuse_a: Optional[Union[bool, _ods_ir]] = None, reuse_b: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: wmma_f16_16x16x128_bf8_bf8(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, *, modC: Optional[Union[Any, _ods_ir]] = None, reuseA: Optional[Union[bool, _ods_ir]] = None, reuseB: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Wave Matrix Multiply-Accumulate (WMMA) with modC and reuse controls. Example: .. code:: mlir // WMMA f32 with fp8 inputs and modC/reuse controls. %r = rocdl.wmma.f32.16x16x64.fp8_fp8 %a, %b, %c, modC = none : (vector<16xi32>, vector<16xi32>, vector<8xf32>) -> vector<8xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.wmma.f16.16x16x128.bf8_bf8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: modC() -> _ods_ir .. py:method:: reuseA() -> _ods_ir .. py:method:: reuseB() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: wmma_f16_16x16x128_bf8_bf8Adaptor(operands: list[Value], attributes: OpAttributeMap) wmma_f16_16x16x128_bf8_bf8Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.wmma.f16.16x16x128.bf8_bf8' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: modC() -> _ods_ir .. py:method:: reuseA() -> _ods_ir .. py:method:: reuseB() -> _ods_ir .. py:function:: wmma_f16_16x16x128_bf8_bf8_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, *, mod_c: Optional[Union[Any, _ods_ir]] = None, reuse_a: Optional[Union[bool, _ods_ir]] = None, reuse_b: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: wmma_f16_16x16x128_bf8_fp8(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, *, modC: Optional[Union[Any, _ods_ir]] = None, reuseA: Optional[Union[bool, _ods_ir]] = None, reuseB: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Wave Matrix Multiply-Accumulate (WMMA) with modC and reuse controls. Example: .. code:: mlir // WMMA f32 with fp8 inputs and modC/reuse controls. %r = rocdl.wmma.f32.16x16x64.fp8_fp8 %a, %b, %c, modC = none : (vector<16xi32>, vector<16xi32>, vector<8xf32>) -> vector<8xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.wmma.f16.16x16x128.bf8_fp8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: modC() -> _ods_ir .. py:method:: reuseA() -> _ods_ir .. py:method:: reuseB() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: wmma_f16_16x16x128_bf8_fp8Adaptor(operands: list[Value], attributes: OpAttributeMap) wmma_f16_16x16x128_bf8_fp8Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.wmma.f16.16x16x128.bf8_fp8' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: modC() -> _ods_ir .. py:method:: reuseA() -> _ods_ir .. py:method:: reuseB() -> _ods_ir .. py:function:: wmma_f16_16x16x128_bf8_fp8_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, *, mod_c: Optional[Union[Any, _ods_ir]] = None, reuse_a: Optional[Union[bool, _ods_ir]] = None, reuse_b: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: wmma_f16_16x16x128_fp8_bf8(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, *, modC: Optional[Union[Any, _ods_ir]] = None, reuseA: Optional[Union[bool, _ods_ir]] = None, reuseB: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Wave Matrix Multiply-Accumulate (WMMA) with modC and reuse controls. Example: .. code:: mlir // WMMA f32 with fp8 inputs and modC/reuse controls. %r = rocdl.wmma.f32.16x16x64.fp8_fp8 %a, %b, %c, modC = none : (vector<16xi32>, vector<16xi32>, vector<8xf32>) -> vector<8xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.wmma.f16.16x16x128.fp8_bf8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: modC() -> _ods_ir .. py:method:: reuseA() -> _ods_ir .. py:method:: reuseB() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: wmma_f16_16x16x128_fp8_bf8Adaptor(operands: list[Value], attributes: OpAttributeMap) wmma_f16_16x16x128_fp8_bf8Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.wmma.f16.16x16x128.fp8_bf8' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: modC() -> _ods_ir .. py:method:: reuseA() -> _ods_ir .. py:method:: reuseB() -> _ods_ir .. py:function:: wmma_f16_16x16x128_fp8_bf8_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, *, mod_c: Optional[Union[Any, _ods_ir]] = None, reuse_a: Optional[Union[bool, _ods_ir]] = None, reuse_b: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: wmma_f16_16x16x128_fp8_fp8(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, *, modC: Optional[Union[Any, _ods_ir]] = None, reuseA: Optional[Union[bool, _ods_ir]] = None, reuseB: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Wave Matrix Multiply-Accumulate (WMMA) with modC and reuse controls. Example: .. code:: mlir // WMMA f32 with fp8 inputs and modC/reuse controls. %r = rocdl.wmma.f32.16x16x64.fp8_fp8 %a, %b, %c, modC = none : (vector<16xi32>, vector<16xi32>, vector<8xf32>) -> vector<8xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.wmma.f16.16x16x128.fp8_fp8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: modC() -> _ods_ir .. py:method:: reuseA() -> _ods_ir .. py:method:: reuseB() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: wmma_f16_16x16x128_fp8_fp8Adaptor(operands: list[Value], attributes: OpAttributeMap) wmma_f16_16x16x128_fp8_fp8Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.wmma.f16.16x16x128.fp8_fp8' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: modC() -> _ods_ir .. py:method:: reuseA() -> _ods_ir .. py:method:: reuseB() -> _ods_ir .. py:function:: wmma_f16_16x16x128_fp8_fp8_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, *, mod_c: Optional[Union[Any, _ods_ir]] = None, reuse_a: Optional[Union[bool, _ods_ir]] = None, reuse_b: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: wmma_f32_16x16x4_f32(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, *, modC: Optional[Union[Any, _ods_ir]] = None, reuseA: Optional[Union[bool, _ods_ir]] = None, reuseB: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Wave Matrix Multiply-Accumulate (WMMA) with modC and reuse controls. Example: .. code:: mlir // WMMA f32 with fp8 inputs and modC/reuse controls. %r = rocdl.wmma.f32.16x16x64.fp8_fp8 %a, %b, %c, modC = none : (vector<16xi32>, vector<16xi32>, vector<8xf32>) -> vector<8xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.wmma.f32.16x16x4.f32' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: modC() -> _ods_ir .. py:method:: reuseA() -> _ods_ir .. py:method:: reuseB() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: wmma_f32_16x16x4_f32Adaptor(operands: list[Value], attributes: OpAttributeMap) wmma_f32_16x16x4_f32Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.wmma.f32.16x16x4.f32' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: modC() -> _ods_ir .. py:method:: reuseA() -> _ods_ir .. py:method:: reuseB() -> _ods_ir .. py:function:: wmma_f32_16x16x4_f32_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, *, mod_c: Optional[Union[Any, _ods_ir]] = None, reuse_a: Optional[Union[bool, _ods_ir]] = None, reuse_b: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: wmma_f32_16x16x16_bf8_bf8(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Wave Matrix Multiply-Accumulate (WMMA) intrinsic. Example: .. code:: mlir // WMMA with f16 inputs and f32 accumulator. %r = rocdl.wmma.f32.16x16x16.f16 %a, %b, %c : (vector<16xf16>, vector<16xf16>, vector<8xf32>) -> vector<8xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.wmma.f32.16x16x16.bf8_bf8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: wmma_f32_16x16x16_bf8_bf8Adaptor(operands: list[Value], attributes: OpAttributeMap) wmma_f32_16x16x16_bf8_bf8Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.wmma.f32.16x16x16.bf8_bf8' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:function:: wmma_f32_16x16x16_bf8_bf8_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: wmma_f32_16x16x16_bf8_fp8(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Wave Matrix Multiply-Accumulate (WMMA) intrinsic. Example: .. code:: mlir // WMMA with f16 inputs and f32 accumulator. %r = rocdl.wmma.f32.16x16x16.f16 %a, %b, %c : (vector<16xf16>, vector<16xf16>, vector<8xf32>) -> vector<8xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.wmma.f32.16x16x16.bf8_fp8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: wmma_f32_16x16x16_bf8_fp8Adaptor(operands: list[Value], attributes: OpAttributeMap) wmma_f32_16x16x16_bf8_fp8Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.wmma.f32.16x16x16.bf8_fp8' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:function:: wmma_f32_16x16x16_bf8_fp8_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: wmma_f32_16x16x16_bf16(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Wave Matrix Multiply-Accumulate (WMMA) intrinsic. Example: .. code:: mlir // WMMA with f16 inputs and f32 accumulator. %r = rocdl.wmma.f32.16x16x16.f16 %a, %b, %c : (vector<16xf16>, vector<16xf16>, vector<8xf32>) -> vector<8xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.wmma.f32.16x16x16.bf16' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: wmma_f32_16x16x16_bf16Adaptor(operands: list[Value], attributes: OpAttributeMap) wmma_f32_16x16x16_bf16Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.wmma.f32.16x16x16.bf16' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:function:: wmma_f32_16x16x16_bf16_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: wmma_f32_16x16x16_f16(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Wave Matrix Multiply-Accumulate (WMMA) intrinsic. Example: .. code:: mlir // WMMA with f16 inputs and f32 accumulator. %r = rocdl.wmma.f32.16x16x16.f16 %a, %b, %c : (vector<16xf16>, vector<16xf16>, vector<8xf32>) -> vector<8xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.wmma.f32.16x16x16.f16' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: wmma_f32_16x16x16_f16Adaptor(operands: list[Value], attributes: OpAttributeMap) wmma_f32_16x16x16_f16Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.wmma.f32.16x16x16.f16' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:function:: wmma_f32_16x16x16_f16_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: wmma_f32_16x16x16_fp8_bf8(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Wave Matrix Multiply-Accumulate (WMMA) intrinsic. Example: .. code:: mlir // WMMA with f16 inputs and f32 accumulator. %r = rocdl.wmma.f32.16x16x16.f16 %a, %b, %c : (vector<16xf16>, vector<16xf16>, vector<8xf32>) -> vector<8xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.wmma.f32.16x16x16.fp8_bf8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: wmma_f32_16x16x16_fp8_bf8Adaptor(operands: list[Value], attributes: OpAttributeMap) wmma_f32_16x16x16_fp8_bf8Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.wmma.f32.16x16x16.fp8_bf8' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:function:: wmma_f32_16x16x16_fp8_bf8_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: wmma_f32_16x16x16_fp8_fp8(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Wave Matrix Multiply-Accumulate (WMMA) intrinsic. Example: .. code:: mlir // WMMA with f16 inputs and f32 accumulator. %r = rocdl.wmma.f32.16x16x16.f16 %a, %b, %c : (vector<16xf16>, vector<16xf16>, vector<8xf32>) -> vector<8xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.wmma.f32.16x16x16.fp8_fp8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: wmma_f32_16x16x16_fp8_fp8Adaptor(operands: list[Value], attributes: OpAttributeMap) wmma_f32_16x16x16_fp8_fp8Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.wmma.f32.16x16x16.fp8_fp8' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:function:: wmma_f32_16x16x16_fp8_fp8_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, *, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: wmma_f32_16x16x32_bf16(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, *, modC: Optional[Union[Any, _ods_ir]] = None, reuseA: Optional[Union[bool, _ods_ir]] = None, reuseB: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Wave Matrix Multiply-Accumulate (WMMA) with modC and reuse controls. Example: .. code:: mlir // WMMA f32 with fp8 inputs and modC/reuse controls. %r = rocdl.wmma.f32.16x16x64.fp8_fp8 %a, %b, %c, modC = none : (vector<16xi32>, vector<16xi32>, vector<8xf32>) -> vector<8xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.wmma.f32.16x16x32.bf16' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: modC() -> _ods_ir .. py:method:: reuseA() -> _ods_ir .. py:method:: reuseB() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: wmma_f32_16x16x32_bf16Adaptor(operands: list[Value], attributes: OpAttributeMap) wmma_f32_16x16x32_bf16Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.wmma.f32.16x16x32.bf16' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: modC() -> _ods_ir .. py:method:: reuseA() -> _ods_ir .. py:method:: reuseB() -> _ods_ir .. py:function:: wmma_f32_16x16x32_bf16_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, *, mod_c: Optional[Union[Any, _ods_ir]] = None, reuse_a: Optional[Union[bool, _ods_ir]] = None, reuse_b: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: wmma_f32_16x16x32_f16(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, *, modC: Optional[Union[Any, _ods_ir]] = None, reuseA: Optional[Union[bool, _ods_ir]] = None, reuseB: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Wave Matrix Multiply-Accumulate (WMMA) with modC and reuse controls. Example: .. code:: mlir // WMMA f32 with fp8 inputs and modC/reuse controls. %r = rocdl.wmma.f32.16x16x64.fp8_fp8 %a, %b, %c, modC = none : (vector<16xi32>, vector<16xi32>, vector<8xf32>) -> vector<8xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.wmma.f32.16x16x32.f16' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: modC() -> _ods_ir .. py:method:: reuseA() -> _ods_ir .. py:method:: reuseB() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: wmma_f32_16x16x32_f16Adaptor(operands: list[Value], attributes: OpAttributeMap) wmma_f32_16x16x32_f16Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.wmma.f32.16x16x32.f16' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: modC() -> _ods_ir .. py:method:: reuseA() -> _ods_ir .. py:method:: reuseB() -> _ods_ir .. py:function:: wmma_f32_16x16x32_f16_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, *, mod_c: Optional[Union[Any, _ods_ir]] = None, reuse_a: Optional[Union[bool, _ods_ir]] = None, reuse_b: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: wmma_f32_16x16x64_bf8_bf8(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, *, modC: Optional[Union[Any, _ods_ir]] = None, reuseA: Optional[Union[bool, _ods_ir]] = None, reuseB: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Wave Matrix Multiply-Accumulate (WMMA) with modC and reuse controls. Example: .. code:: mlir // WMMA f32 with fp8 inputs and modC/reuse controls. %r = rocdl.wmma.f32.16x16x64.fp8_fp8 %a, %b, %c, modC = none : (vector<16xi32>, vector<16xi32>, vector<8xf32>) -> vector<8xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.wmma.f32.16x16x64.bf8_bf8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: modC() -> _ods_ir .. py:method:: reuseA() -> _ods_ir .. py:method:: reuseB() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: wmma_f32_16x16x64_bf8_bf8Adaptor(operands: list[Value], attributes: OpAttributeMap) wmma_f32_16x16x64_bf8_bf8Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.wmma.f32.16x16x64.bf8_bf8' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: modC() -> _ods_ir .. py:method:: reuseA() -> _ods_ir .. py:method:: reuseB() -> _ods_ir .. py:function:: wmma_f32_16x16x64_bf8_bf8_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, *, mod_c: Optional[Union[Any, _ods_ir]] = None, reuse_a: Optional[Union[bool, _ods_ir]] = None, reuse_b: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: wmma_f32_16x16x64_bf8_fp8(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, *, modC: Optional[Union[Any, _ods_ir]] = None, reuseA: Optional[Union[bool, _ods_ir]] = None, reuseB: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Wave Matrix Multiply-Accumulate (WMMA) with modC and reuse controls. Example: .. code:: mlir // WMMA f32 with fp8 inputs and modC/reuse controls. %r = rocdl.wmma.f32.16x16x64.fp8_fp8 %a, %b, %c, modC = none : (vector<16xi32>, vector<16xi32>, vector<8xf32>) -> vector<8xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.wmma.f32.16x16x64.bf8_fp8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: modC() -> _ods_ir .. py:method:: reuseA() -> _ods_ir .. py:method:: reuseB() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: wmma_f32_16x16x64_bf8_fp8Adaptor(operands: list[Value], attributes: OpAttributeMap) wmma_f32_16x16x64_bf8_fp8Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.wmma.f32.16x16x64.bf8_fp8' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: modC() -> _ods_ir .. py:method:: reuseA() -> _ods_ir .. py:method:: reuseB() -> _ods_ir .. py:function:: wmma_f32_16x16x64_bf8_fp8_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, *, mod_c: Optional[Union[Any, _ods_ir]] = None, reuse_a: Optional[Union[bool, _ods_ir]] = None, reuse_b: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: wmma_f32_16x16x64_fp8_bf8(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, *, modC: Optional[Union[Any, _ods_ir]] = None, reuseA: Optional[Union[bool, _ods_ir]] = None, reuseB: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Wave Matrix Multiply-Accumulate (WMMA) with modC and reuse controls. Example: .. code:: mlir // WMMA f32 with fp8 inputs and modC/reuse controls. %r = rocdl.wmma.f32.16x16x64.fp8_fp8 %a, %b, %c, modC = none : (vector<16xi32>, vector<16xi32>, vector<8xf32>) -> vector<8xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.wmma.f32.16x16x64.fp8_bf8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: modC() -> _ods_ir .. py:method:: reuseA() -> _ods_ir .. py:method:: reuseB() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: wmma_f32_16x16x64_fp8_bf8Adaptor(operands: list[Value], attributes: OpAttributeMap) wmma_f32_16x16x64_fp8_bf8Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.wmma.f32.16x16x64.fp8_bf8' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: modC() -> _ods_ir .. py:method:: reuseA() -> _ods_ir .. py:method:: reuseB() -> _ods_ir .. py:function:: wmma_f32_16x16x64_fp8_bf8_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, *, mod_c: Optional[Union[Any, _ods_ir]] = None, reuse_a: Optional[Union[bool, _ods_ir]] = None, reuse_b: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: wmma_f32_16x16x64_fp8_fp8(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, *, modC: Optional[Union[Any, _ods_ir]] = None, reuseA: Optional[Union[bool, _ods_ir]] = None, reuseB: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Wave Matrix Multiply-Accumulate (WMMA) with modC and reuse controls. Example: .. code:: mlir // WMMA f32 with fp8 inputs and modC/reuse controls. %r = rocdl.wmma.f32.16x16x64.fp8_fp8 %a, %b, %c, modC = none : (vector<16xi32>, vector<16xi32>, vector<8xf32>) -> vector<8xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.wmma.f32.16x16x64.fp8_fp8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: modC() -> _ods_ir .. py:method:: reuseA() -> _ods_ir .. py:method:: reuseB() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: wmma_f32_16x16x64_fp8_fp8Adaptor(operands: list[Value], attributes: OpAttributeMap) wmma_f32_16x16x64_fp8_fp8Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.wmma.f32.16x16x64.fp8_fp8' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: modC() -> _ods_ir .. py:method:: reuseA() -> _ods_ir .. py:method:: reuseB() -> _ods_ir .. py:function:: wmma_f32_16x16x64_fp8_fp8_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, *, mod_c: Optional[Union[Any, _ods_ir]] = None, reuse_a: Optional[Union[bool, _ods_ir]] = None, reuse_b: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: wmma_f32_16x16x128_bf8_bf8(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, *, modC: Optional[Union[Any, _ods_ir]] = None, reuseA: Optional[Union[bool, _ods_ir]] = None, reuseB: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Wave Matrix Multiply-Accumulate (WMMA) with modC and reuse controls. Example: .. code:: mlir // WMMA f32 with fp8 inputs and modC/reuse controls. %r = rocdl.wmma.f32.16x16x64.fp8_fp8 %a, %b, %c, modC = none : (vector<16xi32>, vector<16xi32>, vector<8xf32>) -> vector<8xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.wmma.f32.16x16x128.bf8_bf8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: modC() -> _ods_ir .. py:method:: reuseA() -> _ods_ir .. py:method:: reuseB() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: wmma_f32_16x16x128_bf8_bf8Adaptor(operands: list[Value], attributes: OpAttributeMap) wmma_f32_16x16x128_bf8_bf8Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.wmma.f32.16x16x128.bf8_bf8' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: modC() -> _ods_ir .. py:method:: reuseA() -> _ods_ir .. py:method:: reuseB() -> _ods_ir .. py:function:: wmma_f32_16x16x128_bf8_bf8_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, *, mod_c: Optional[Union[Any, _ods_ir]] = None, reuse_a: Optional[Union[bool, _ods_ir]] = None, reuse_b: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: wmma_f32_16x16x128_bf8_fp8(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, *, modC: Optional[Union[Any, _ods_ir]] = None, reuseA: Optional[Union[bool, _ods_ir]] = None, reuseB: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Wave Matrix Multiply-Accumulate (WMMA) with modC and reuse controls. Example: .. code:: mlir // WMMA f32 with fp8 inputs and modC/reuse controls. %r = rocdl.wmma.f32.16x16x64.fp8_fp8 %a, %b, %c, modC = none : (vector<16xi32>, vector<16xi32>, vector<8xf32>) -> vector<8xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.wmma.f32.16x16x128.bf8_fp8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: modC() -> _ods_ir .. py:method:: reuseA() -> _ods_ir .. py:method:: reuseB() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: wmma_f32_16x16x128_bf8_fp8Adaptor(operands: list[Value], attributes: OpAttributeMap) wmma_f32_16x16x128_bf8_fp8Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.wmma.f32.16x16x128.bf8_fp8' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: modC() -> _ods_ir .. py:method:: reuseA() -> _ods_ir .. py:method:: reuseB() -> _ods_ir .. py:function:: wmma_f32_16x16x128_bf8_fp8_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, *, mod_c: Optional[Union[Any, _ods_ir]] = None, reuse_a: Optional[Union[bool, _ods_ir]] = None, reuse_b: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: wmma_f32_16x16x128_fp8_bf8(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, *, modC: Optional[Union[Any, _ods_ir]] = None, reuseA: Optional[Union[bool, _ods_ir]] = None, reuseB: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Wave Matrix Multiply-Accumulate (WMMA) with modC and reuse controls. Example: .. code:: mlir // WMMA f32 with fp8 inputs and modC/reuse controls. %r = rocdl.wmma.f32.16x16x64.fp8_fp8 %a, %b, %c, modC = none : (vector<16xi32>, vector<16xi32>, vector<8xf32>) -> vector<8xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.wmma.f32.16x16x128.fp8_bf8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: modC() -> _ods_ir .. py:method:: reuseA() -> _ods_ir .. py:method:: reuseB() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: wmma_f32_16x16x128_fp8_bf8Adaptor(operands: list[Value], attributes: OpAttributeMap) wmma_f32_16x16x128_fp8_bf8Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.wmma.f32.16x16x128.fp8_bf8' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: modC() -> _ods_ir .. py:method:: reuseA() -> _ods_ir .. py:method:: reuseB() -> _ods_ir .. py:function:: wmma_f32_16x16x128_fp8_bf8_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, *, mod_c: Optional[Union[Any, _ods_ir]] = None, reuse_a: Optional[Union[bool, _ods_ir]] = None, reuse_b: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: wmma_f32_16x16x128_fp8_fp8(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, *, modC: Optional[Union[Any, _ods_ir]] = None, reuseA: Optional[Union[bool, _ods_ir]] = None, reuseB: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Wave Matrix Multiply-Accumulate (WMMA) with modC and reuse controls. Example: .. code:: mlir // WMMA f32 with fp8 inputs and modC/reuse controls. %r = rocdl.wmma.f32.16x16x64.fp8_fp8 %a, %b, %c, modC = none : (vector<16xi32>, vector<16xi32>, vector<8xf32>) -> vector<8xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.wmma.f32.16x16x128.fp8_fp8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: modC() -> _ods_ir .. py:method:: reuseA() -> _ods_ir .. py:method:: reuseB() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: wmma_f32_16x16x128_fp8_fp8Adaptor(operands: list[Value], attributes: OpAttributeMap) wmma_f32_16x16x128_fp8_fp8Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.wmma.f32.16x16x128.fp8_fp8' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: modC() -> _ods_ir .. py:method:: reuseA() -> _ods_ir .. py:method:: reuseB() -> _ods_ir .. py:function:: wmma_f32_16x16x128_fp8_fp8_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, *, mod_c: Optional[Union[Any, _ods_ir]] = None, reuse_a: Optional[Union[bool, _ods_ir]] = None, reuse_b: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: wmma_i32_16x16x16_iu4(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, *, signA: Optional[Union[bool, _ods_ir]] = None, signB: Optional[Union[bool, _ods_ir]] = None, clamp: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Wave Matrix Multiply-Accumulate (WMMA) for integer types with sign and clamp control. Example: .. code:: mlir // WMMA i32 with unsigned i8 inputs. %r = rocdl.wmma.i32.16x16x16.iu8 %a, %b, %c {signA = false, signB = false, clamp = false} : (vector<4xi32>, vector<4xi32>, vector<8xi32>) -> vector<8xi32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.wmma.i32.16x16x16.iu4' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: signA() -> _ods_ir .. py:method:: signB() -> _ods_ir .. py:method:: clamp() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: wmma_i32_16x16x16_iu4Adaptor(operands: list[Value], attributes: OpAttributeMap) wmma_i32_16x16x16_iu4Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.wmma.i32.16x16x16.iu4' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: signA() -> _ods_ir .. py:method:: signB() -> _ods_ir .. py:method:: clamp() -> _ods_ir .. py:function:: wmma_i32_16x16x16_iu4_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, *, sign_a: Optional[Union[bool, _ods_ir]] = None, sign_b: Optional[Union[bool, _ods_ir]] = None, clamp: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: wmma_i32_16x16x16_iu8(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, *, signA: Optional[Union[bool, _ods_ir]] = None, signB: Optional[Union[bool, _ods_ir]] = None, clamp: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Wave Matrix Multiply-Accumulate (WMMA) for integer types with sign and clamp control. Example: .. code:: mlir // WMMA i32 with unsigned i8 inputs. %r = rocdl.wmma.i32.16x16x16.iu8 %a, %b, %c {signA = false, signB = false, clamp = false} : (vector<4xi32>, vector<4xi32>, vector<8xi32>) -> vector<8xi32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.wmma.i32.16x16x16.iu8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: signA() -> _ods_ir .. py:method:: signB() -> _ods_ir .. py:method:: clamp() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: wmma_i32_16x16x16_iu8Adaptor(operands: list[Value], attributes: OpAttributeMap) wmma_i32_16x16x16_iu8Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.wmma.i32.16x16x16.iu8' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: signA() -> _ods_ir .. py:method:: signB() -> _ods_ir .. py:method:: clamp() -> _ods_ir .. py:function:: wmma_i32_16x16x16_iu8_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, *, sign_a: Optional[Union[bool, _ods_ir]] = None, sign_b: Optional[Union[bool, _ods_ir]] = None, clamp: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: wmma_i32_16x16x32_iu4(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, *, signA: Optional[Union[bool, _ods_ir]] = None, signB: Optional[Union[bool, _ods_ir]] = None, clamp: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Wave Matrix Multiply-Accumulate (WMMA) for integer types with sign and clamp control. Example: .. code:: mlir // WMMA i32 with unsigned i8 inputs. %r = rocdl.wmma.i32.16x16x16.iu8 %a, %b, %c {signA = false, signB = false, clamp = false} : (vector<4xi32>, vector<4xi32>, vector<8xi32>) -> vector<8xi32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.wmma.i32.16x16x32.iu4' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: signA() -> _ods_ir .. py:method:: signB() -> _ods_ir .. py:method:: clamp() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: wmma_i32_16x16x32_iu4Adaptor(operands: list[Value], attributes: OpAttributeMap) wmma_i32_16x16x32_iu4Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.wmma.i32.16x16x32.iu4' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: signA() -> _ods_ir .. py:method:: signB() -> _ods_ir .. py:method:: clamp() -> _ods_ir .. py:function:: wmma_i32_16x16x32_iu4_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, *, sign_a: Optional[Union[bool, _ods_ir]] = None, sign_b: Optional[Union[bool, _ods_ir]] = None, clamp: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: wmma_i32_16x16x64_iu8(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, *, signA: Optional[Union[bool, _ods_ir]] = None, signB: Optional[Union[bool, _ods_ir]] = None, reuseA: Optional[Union[bool, _ods_ir]] = None, reuseB: Optional[Union[bool, _ods_ir]] = None, clamp: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Wave Matrix Multiply-Accumulate (WMMA) for integer types with sign, reuse, and clamp controls. Example: .. code:: mlir // WMMA i32 with unsigned i8 inputs and reuse controls. %r = rocdl.wmma.i32.16x16x64.iu8 %a, %b, %c {signA = false, signB = false, reuseA = false, reuseB = false, clamp = false} : (vector<8xi32>, vector<8xi32>, vector<8xi32>) -> vector<8xi32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.wmma.i32.16x16x64.iu8' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: signA() -> _ods_ir .. py:method:: signB() -> _ods_ir .. py:method:: reuseA() -> _ods_ir .. py:method:: reuseB() -> _ods_ir .. py:method:: clamp() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: wmma_i32_16x16x64_iu8Adaptor(operands: list[Value], attributes: OpAttributeMap) wmma_i32_16x16x64_iu8Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.wmma.i32.16x16x64.iu8' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: signA() -> _ods_ir .. py:method:: signB() -> _ods_ir .. py:method:: reuseA() -> _ods_ir .. py:method:: reuseB() -> _ods_ir .. py:method:: clamp() -> _ods_ir .. py:function:: wmma_i32_16x16x64_iu8_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, *, sign_a: Optional[Union[bool, _ods_ir]] = None, sign_b: Optional[Union[bool, _ods_ir]] = None, reuse_a: Optional[Union[bool, _ods_ir]] = None, reuse_b: Optional[Union[bool, _ods_ir]] = None, clamp: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: wmma_scale16_f32_16x16x128_f8f6f4(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, scaleA: _ods_ir[_ods_ir], scaleB: _ods_ir[_ods_ir], *, fmtA: Optional[Union[Any, _ods_ir]] = None, fmtB: Optional[Union[Any, _ods_ir]] = None, modC: Optional[Union[Any, _ods_ir]] = None, scaleAType: Optional[Union[Any, _ods_ir]] = None, fmtScaleA: Optional[Union[Any, _ods_ir]] = None, scaleBType: Optional[Union[Any, _ods_ir]] = None, fmtScaleB: Optional[Union[Any, _ods_ir]] = None, reuseA: Optional[Union[bool, _ods_ir]] = None, reuseB: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Scaled Wave Matrix Multiply-Accumulate (WMMA) with per-operand scaling. Example: .. code:: mlir // Scaled WMMA with f8f6f4 format inputs. %r = rocdl.wmma.scale.f32.16x16x128.f8f6f4 %a, %b, %c, %scaleA, %scaleB fmtA = fp8_e4m3, fmtB = fp8_e4m3, modC = none, scaleAType = row0, fmtScaleA = e8, scaleBType = row0, fmtScaleB = e8 : (vector<16xi32>, vector<16xi32>, vector<8xf32>, i32, i32) -> vector<8xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.wmma.scale16.f32.16x16x128.f8f6f4' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: scaleA() -> _ods_ir[_ods_ir] .. py:method:: scaleB() -> _ods_ir[_ods_ir] .. py:method:: fmtA() -> _ods_ir .. py:method:: fmtB() -> _ods_ir .. py:method:: modC() -> _ods_ir .. py:method:: scaleAType() -> _ods_ir .. py:method:: fmtScaleA() -> _ods_ir .. py:method:: scaleBType() -> _ods_ir .. py:method:: fmtScaleB() -> _ods_ir .. py:method:: reuseA() -> _ods_ir .. py:method:: reuseB() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: wmma_scale16_f32_16x16x128_f8f6f4Adaptor(operands: list[Value], attributes: OpAttributeMap) wmma_scale16_f32_16x16x128_f8f6f4Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.wmma.scale16.f32.16x16x128.f8f6f4' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: scaleA() -> _ods_ir[_ods_ir] .. py:method:: scaleB() -> _ods_ir[_ods_ir] .. py:method:: fmtA() -> _ods_ir .. py:method:: fmtB() -> _ods_ir .. py:method:: modC() -> _ods_ir .. py:method:: scaleAType() -> _ods_ir .. py:method:: fmtScaleA() -> _ods_ir .. py:method:: scaleBType() -> _ods_ir .. py:method:: fmtScaleB() -> _ods_ir .. py:method:: reuseA() -> _ods_ir .. py:method:: reuseB() -> _ods_ir .. py:function:: wmma_scale16_f32_16x16x128_f8f6f4_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, scale_a: _ods_ir[_ods_ir], scale_b: _ods_ir[_ods_ir], *, fmt_a: Optional[Union[Any, _ods_ir]] = None, fmt_b: Optional[Union[Any, _ods_ir]] = None, mod_c: Optional[Union[Any, _ods_ir]] = None, scale_a_type: Optional[Union[Any, _ods_ir]] = None, fmt_scale_a: Optional[Union[Any, _ods_ir]] = None, scale_b_type: Optional[Union[Any, _ods_ir]] = None, fmt_scale_b: Optional[Union[Any, _ods_ir]] = None, reuse_a: Optional[Union[bool, _ods_ir]] = None, reuse_b: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: wmma_scale16_f32_32x16x128_f4(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, scaleA: _ods_ir[_ods_ir], scaleB: _ods_ir[_ods_ir], *, modC: Optional[Union[Any, _ods_ir]] = None, scaleAType: Optional[Union[Any, _ods_ir]] = None, fmtScaleA: Optional[Union[Any, _ods_ir]] = None, scaleBType: Optional[Union[Any, _ods_ir]] = None, fmtScaleB: Optional[Union[Any, _ods_ir]] = None, reuseA: Optional[Union[bool, _ods_ir]] = None, reuseB: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Scaled Wave Matrix Multiply-Accumulate (WMMA) for F4 format inputs. Example: .. code:: mlir // Scaled WMMA with f4 format inputs. %r = rocdl.wmma.scale.f32.16x16x128.f4 %a, %b, %c, %scaleA, %scaleB modC = none, scaleAType = row0, fmtScaleA = e8, scaleBType = row0, fmtScaleB = e8 : (vector<8xi32>, vector<8xi32>, vector<8xf32>, i32, i32) -> vector<8xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.wmma.scale16.f32.32x16x128.f4' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: scaleA() -> _ods_ir[_ods_ir] .. py:method:: scaleB() -> _ods_ir[_ods_ir] .. py:method:: modC() -> _ods_ir .. py:method:: scaleAType() -> _ods_ir .. py:method:: fmtScaleA() -> _ods_ir .. py:method:: scaleBType() -> _ods_ir .. py:method:: fmtScaleB() -> _ods_ir .. py:method:: reuseA() -> _ods_ir .. py:method:: reuseB() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: wmma_scale16_f32_32x16x128_f4Adaptor(operands: list[Value], attributes: OpAttributeMap) wmma_scale16_f32_32x16x128_f4Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.wmma.scale16.f32.32x16x128.f4' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: scaleA() -> _ods_ir[_ods_ir] .. py:method:: scaleB() -> _ods_ir[_ods_ir] .. py:method:: modC() -> _ods_ir .. py:method:: scaleAType() -> _ods_ir .. py:method:: fmtScaleA() -> _ods_ir .. py:method:: scaleBType() -> _ods_ir .. py:method:: fmtScaleB() -> _ods_ir .. py:method:: reuseA() -> _ods_ir .. py:method:: reuseB() -> _ods_ir .. py:function:: wmma_scale16_f32_32x16x128_f4_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, scale_a: _ods_ir[_ods_ir], scale_b: _ods_ir[_ods_ir], *, mod_c: Optional[Union[Any, _ods_ir]] = None, scale_a_type: Optional[Union[Any, _ods_ir]] = None, fmt_scale_a: Optional[Union[Any, _ods_ir]] = None, scale_b_type: Optional[Union[Any, _ods_ir]] = None, fmt_scale_b: Optional[Union[Any, _ods_ir]] = None, reuse_a: Optional[Union[bool, _ods_ir]] = None, reuse_b: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: wmma_scale_f32_16x16x128_f8f6f4(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, scaleA: _ods_ir[_ods_ir], scaleB: _ods_ir[_ods_ir], *, fmtA: Optional[Union[Any, _ods_ir]] = None, fmtB: Optional[Union[Any, _ods_ir]] = None, modC: Optional[Union[Any, _ods_ir]] = None, scaleAType: Optional[Union[Any, _ods_ir]] = None, fmtScaleA: Optional[Union[Any, _ods_ir]] = None, scaleBType: Optional[Union[Any, _ods_ir]] = None, fmtScaleB: Optional[Union[Any, _ods_ir]] = None, reuseA: Optional[Union[bool, _ods_ir]] = None, reuseB: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Scaled Wave Matrix Multiply-Accumulate (WMMA) with per-operand scaling. Example: .. code:: mlir // Scaled WMMA with f8f6f4 format inputs. %r = rocdl.wmma.scale.f32.16x16x128.f8f6f4 %a, %b, %c, %scaleA, %scaleB fmtA = fp8_e4m3, fmtB = fp8_e4m3, modC = none, scaleAType = row0, fmtScaleA = e8, scaleBType = row0, fmtScaleB = e8 : (vector<16xi32>, vector<16xi32>, vector<8xf32>, i32, i32) -> vector<8xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.wmma.scale.f32.16x16x128.f8f6f4' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: scaleA() -> _ods_ir[_ods_ir] .. py:method:: scaleB() -> _ods_ir[_ods_ir] .. py:method:: fmtA() -> _ods_ir .. py:method:: fmtB() -> _ods_ir .. py:method:: modC() -> _ods_ir .. py:method:: scaleAType() -> _ods_ir .. py:method:: fmtScaleA() -> _ods_ir .. py:method:: scaleBType() -> _ods_ir .. py:method:: fmtScaleB() -> _ods_ir .. py:method:: reuseA() -> _ods_ir .. py:method:: reuseB() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: wmma_scale_f32_16x16x128_f8f6f4Adaptor(operands: list[Value], attributes: OpAttributeMap) wmma_scale_f32_16x16x128_f8f6f4Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.wmma.scale.f32.16x16x128.f8f6f4' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: scaleA() -> _ods_ir[_ods_ir] .. py:method:: scaleB() -> _ods_ir[_ods_ir] .. py:method:: fmtA() -> _ods_ir .. py:method:: fmtB() -> _ods_ir .. py:method:: modC() -> _ods_ir .. py:method:: scaleAType() -> _ods_ir .. py:method:: fmtScaleA() -> _ods_ir .. py:method:: scaleBType() -> _ods_ir .. py:method:: fmtScaleB() -> _ods_ir .. py:method:: reuseA() -> _ods_ir .. py:method:: reuseB() -> _ods_ir .. py:function:: wmma_scale_f32_16x16x128_f8f6f4_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, scale_a: _ods_ir[_ods_ir], scale_b: _ods_ir[_ods_ir], *, fmt_a: Optional[Union[Any, _ods_ir]] = None, fmt_b: Optional[Union[Any, _ods_ir]] = None, mod_c: Optional[Union[Any, _ods_ir]] = None, scale_a_type: Optional[Union[Any, _ods_ir]] = None, fmt_scale_a: Optional[Union[Any, _ods_ir]] = None, scale_b_type: Optional[Union[Any, _ods_ir]] = None, fmt_scale_b: Optional[Union[Any, _ods_ir]] = None, reuse_a: Optional[Union[bool, _ods_ir]] = None, reuse_b: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir .. py:class:: wmma_scale_f32_32x16x128_f4(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, scaleA: _ods_ir[_ods_ir], scaleB: _ods_ir[_ods_ir], *, modC: Optional[Union[Any, _ods_ir]] = None, scaleAType: Optional[Union[Any, _ods_ir]] = None, fmtScaleA: Optional[Union[Any, _ods_ir]] = None, scaleBType: Optional[Union[Any, _ods_ir]] = None, fmtScaleB: Optional[Union[Any, _ods_ir]] = None, reuseA: Optional[Union[bool, _ods_ir]] = None, reuseB: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) Bases: :py:obj:`_ods_ir` Scaled Wave Matrix Multiply-Accumulate (WMMA) for F4 format inputs. Example: .. code:: mlir // Scaled WMMA with f4 format inputs. %r = rocdl.wmma.scale.f32.16x16x128.f4 %a, %b, %c, %scaleA, %scaleB modC = none, scaleAType = row0, fmtScaleA = e8, scaleBType = row0, fmtScaleB = e8 : (vector<8xi32>, vector<8xi32>, vector<8xf32>, i32, i32) -> vector<8xf32> .. py:attribute:: OPERATION_NAME :value: 'rocdl.wmma.scale.f32.32x16x128.f4' .. py:attribute:: _ODS_REGIONS :value: (0, True) .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: scaleA() -> _ods_ir[_ods_ir] .. py:method:: scaleB() -> _ods_ir[_ods_ir] .. py:method:: modC() -> _ods_ir .. py:method:: scaleAType() -> _ods_ir .. py:method:: fmtScaleA() -> _ods_ir .. py:method:: scaleBType() -> _ods_ir .. py:method:: fmtScaleB() -> _ods_ir .. py:method:: reuseA() -> _ods_ir .. py:method:: reuseB() -> _ods_ir .. py:method:: res() -> _ods_ir .. py:class:: wmma_scale_f32_32x16x128_f4Adaptor(operands: list[Value], attributes: OpAttributeMap) wmma_scale_f32_32x16x128_f4Adaptor(operands: list[Value], opview: OpView) Bases: :py:obj:`_ods_ir` .. py:attribute:: OPERATION_NAME :value: 'rocdl.wmma.scale.f32.32x16x128.f4' .. py:method:: a() -> _ods_ir .. py:method:: b() -> _ods_ir .. py:method:: c() -> _ods_ir .. py:method:: scaleA() -> _ods_ir[_ods_ir] .. py:method:: scaleB() -> _ods_ir[_ods_ir] .. py:method:: modC() -> _ods_ir .. py:method:: scaleAType() -> _ods_ir .. py:method:: fmtScaleA() -> _ods_ir .. py:method:: scaleBType() -> _ods_ir .. py:method:: fmtScaleB() -> _ods_ir .. py:method:: reuseA() -> _ods_ir .. py:method:: reuseB() -> _ods_ir .. py:function:: wmma_scale_f32_32x16x128_f4_(res: _ods_ir, a: _ods_ir, b: _ods_ir, c: _ods_ir, scale_a: _ods_ir[_ods_ir], scale_b: _ods_ir[_ods_ir], *, mod_c: Optional[Union[Any, _ods_ir]] = None, scale_a_type: Optional[Union[Any, _ods_ir]] = None, fmt_scale_a: Optional[Union[Any, _ods_ir]] = None, scale_b_type: Optional[Union[Any, _ods_ir]] = None, fmt_scale_b: Optional[Union[Any, _ods_ir]] = None, reuse_a: Optional[Union[bool, _ods_ir]] = None, reuse_b: Optional[Union[bool, _ods_ir]] = None, loc: Optional[_ods_ir] = None, ip: Optional[_ods_ir] = None) -> _ods_ir