MLIR  20.0.0git
TensorToSPIRV.h
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1 //===- TensorToSPIRV.h - Tensor to SPIR-V Patterns --------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Provides patterns to convert Tensor dialect to SPIR-V dialect.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef MLIR_CONVERSION_TENSORTOSPIRV_TENSORTOSPIRV_H
14 #define MLIR_CONVERSION_TENSORTOSPIRV_TENSORTOSPIRV_H
15 
17 
18 namespace mlir {
19 class SPIRVTypeConverter;
20 
21 /// Appends to a pattern list additional patterns for translating tensor ops
22 /// to SPIR-V ops.
23 ///
24 /// Note: Normally tensors will be stored in buffers before converting to
25 /// SPIR-V, given that is how a large amount of data is sent to the GPU.
26 /// However, SPIR-V supports converting from tensors directly too. This is
27 /// for the cases where the tensor just contains a small amount of elements
28 /// and it makes sense to directly inline them as a small data array in the
29 /// shader. To handle this, internally the conversion might create new local
30 /// variables. SPIR-V consumers in GPU drivers may or may not optimize that
31 /// away. So this has implications over register pressure. Therefore, a
32 /// threshold is used to control when the patterns should kick in.
33 void populateTensorToSPIRVPatterns(const SPIRVTypeConverter &typeConverter,
34  int64_t byteCountThreshold,
35  RewritePatternSet &patterns);
36 
37 } // namespace mlir
38 
39 #endif // MLIR_CONVERSION_TENSORTOSPIRV_TENSORTOSPIRV_H
Include the generated interface declarations.
void populateTensorToSPIRVPatterns(const SPIRVTypeConverter &typeConverter, int64_t byteCountThreshold, RewritePatternSet &patterns)
Appends to a pattern list additional patterns for translating tensor ops to SPIR-V ops.