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Value | mlir::x86vector::avx2::inline_asm::mm256BlendPsAsm (ImplicitLocOpBuilder &b, Value v1, Value v2, uint8_t mask) |
| Methods in the inline_asm namespace emit calls to LLVM::InlineAsmOp. More...
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Value | mlir::x86vector::avx2::intrin::mm256UnpackLoPs (ImplicitLocOpBuilder &b, Value v1, Value v2) |
| Methods in the intrin namespace emulate clang's impl. of X86 intrinsics. More...
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Value | mlir::x86vector::avx2::intrin::mm256UnpackHiPs (ImplicitLocOpBuilder &b, Value v1, Value v2) |
| Lower to vector.shuffle v1, v2, [0, 8, 1, 9, 4, 12, 5, 13]. More...
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Value | mlir::x86vector::avx2::intrin::mm256ShufflePs (ImplicitLocOpBuilder &b, Value v1, Value v2, uint8_t mask) |
| a a b b a a b b Take an 8 bit mask, 2 bit for each position of a[0, 3) and b[0, 4): 0:127 | 128:255 b01 b23 C8 D8 | b01+4 b23+4 C8+4 D8+4 More...
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Value | mlir::x86vector::avx2::intrin::mm256Permute2f128Ps (ImplicitLocOpBuilder &b, Value v1, Value v2, uint8_t mask) |
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Value | mlir::x86vector::avx2::intrin::mm256BlendPs (ImplicitLocOpBuilder &b, Value v1, Value v2, uint8_t mask) |
| If bit i of mask is zero, take f32@i from v1 else take it from v2. More...
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void | mlir::x86vector::avx2::transpose4x8xf32 (ImplicitLocOpBuilder &ib, MutableArrayRef< Value > vs) |
| Generic lowerings may either use intrin or inline_asm depending on needs. More...
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void | mlir::x86vector::avx2::transpose8x8xf32 (ImplicitLocOpBuilder &ib, MutableArrayRef< Value > vs) |
| 8x8xf32-specific AVX2 transpose lowering. More...
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void | mlir::x86vector::avx2::populateSpecializedTransposeLoweringPatterns (RewritePatternSet &patterns, LoweringOptions options=LoweringOptions(), int benefit=10) |
| Insert specialized transpose lowering patterns. More...
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void | mlir::populateX86VectorLegalizeForLLVMExportPatterns (const LLVMTypeConverter &converter, RewritePatternSet &patterns) |
| Collect a set of patterns to lower X86Vector ops to ops that map to LLVM intrinsics. More...
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void | mlir::configureX86VectorLegalizeForExportTarget (LLVMConversionTarget &target) |
| Configure the target to support lowering X86Vector ops to ops that map to LLVM intrinsics. More...
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