MLIR  19.0.0git
Target.cpp
Go to the documentation of this file.
1 //===- Target.cpp - MLIR LLVM ROCDL target compilation ----------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This files defines ROCDL target related functions including registration
10 // calls for the `#rocdl.target` compilation attribute.
11 //
12 //===----------------------------------------------------------------------===//
13 
15 
21 
22 #include "llvm/IR/Constants.h"
23 #include "llvm/MC/MCAsmBackend.h"
24 #include "llvm/MC/MCAsmInfo.h"
25 #include "llvm/MC/MCCodeEmitter.h"
26 #include "llvm/MC/MCContext.h"
27 #include "llvm/MC/MCInstrInfo.h"
28 #include "llvm/MC/MCObjectFileInfo.h"
29 #include "llvm/MC/MCObjectWriter.h"
30 #include "llvm/MC/MCParser/MCTargetAsmParser.h"
31 #include "llvm/MC/MCRegisterInfo.h"
32 #include "llvm/MC/MCStreamer.h"
33 #include "llvm/MC/MCSubtargetInfo.h"
34 #include "llvm/MC/TargetRegistry.h"
35 #include "llvm/Support/FileSystem.h"
36 #include "llvm/Support/FileUtilities.h"
37 #include "llvm/Support/Path.h"
38 #include "llvm/Support/Program.h"
39 #include "llvm/Support/SourceMgr.h"
40 #include "llvm/Support/TargetSelect.h"
41 #include "llvm/TargetParser/TargetParser.h"
42 
43 #include <cstdlib>
44 #include <optional>
45 
46 using namespace mlir;
47 using namespace mlir::ROCDL;
48 
49 #ifndef __DEFAULT_ROCM_PATH__
50 #define __DEFAULT_ROCM_PATH__ ""
51 #endif
52 
53 namespace {
54 // Implementation of the `TargetAttrInterface` model.
55 class ROCDLTargetAttrImpl
56  : public gpu::TargetAttrInterface::FallbackModel<ROCDLTargetAttrImpl> {
57 public:
58  std::optional<SmallVector<char, 0>>
59  serializeToObject(Attribute attribute, Operation *module,
60  const gpu::TargetOptions &options) const;
61 
62  Attribute createObject(Attribute attribute,
63  const SmallVector<char, 0> &object,
64  const gpu::TargetOptions &options) const;
65 };
66 } // namespace
67 
68 // Register the ROCDL dialect, the ROCDL translation and the target interface.
70  DialectRegistry &registry) {
71  registry.addExtension(+[](MLIRContext *ctx, ROCDL::ROCDLDialect *dialect) {
72  ROCDLTargetAttr::attachInterface<ROCDLTargetAttrImpl>(*ctx);
73  });
74 }
75 
77  MLIRContext &context) {
78  DialectRegistry registry;
80  context.appendDialectRegistry(registry);
81 }
82 
83 // Search for the ROCM path.
85  if (const char *var = std::getenv("ROCM_PATH"))
86  return var;
87  if (const char *var = std::getenv("ROCM_ROOT"))
88  return var;
89  if (const char *var = std::getenv("ROCM_HOME"))
90  return var;
91  return __DEFAULT_ROCM_PATH__;
92 }
93 
95  Operation &module, ROCDLTargetAttr target,
96  const gpu::TargetOptions &targetOptions)
97  : ModuleToObject(module, target.getTriple(), target.getChip(),
98  target.getFeatures(), target.getO()),
99  target(target), toolkitPath(targetOptions.getToolkitPath()),
100  fileList(targetOptions.getLinkFiles()) {
101 
102  // If `targetOptions` has an empty toolkitPath use `getROCMPath`
103  if (toolkitPath.empty())
105 
106  // Append the files in the target attribute.
107  if (ArrayAttr files = target.getLink())
108  for (Attribute attr : files.getValue())
109  if (auto file = dyn_cast<StringAttr>(attr))
110  fileList.push_back(file.str());
111 }
112 
114  static llvm::once_flag initializeBackendOnce;
115  llvm::call_once(initializeBackendOnce, []() {
116  // If the `AMDGPU` LLVM target was built, initialize it.
117 #if MLIR_ENABLE_ROCM_CONVERSIONS
118  LLVMInitializeAMDGPUTarget();
119  LLVMInitializeAMDGPUTargetInfo();
120  LLVMInitializeAMDGPUTargetMC();
121  LLVMInitializeAMDGPUAsmParser();
122  LLVMInitializeAMDGPUAsmPrinter();
123 #endif
124  });
125 }
126 
127 ROCDLTargetAttr SerializeGPUModuleBase::getTarget() const { return target; }
128 
130 
132  return fileList;
133 }
134 
136  if (libs == AMDGCNLibraries::None)
137  return success();
138  StringRef pathRef = getToolkitPath();
139 
140  // Get the path for the device libraries
141  SmallString<256> path;
142  path.insert(path.begin(), pathRef.begin(), pathRef.end());
143  llvm::sys::path::append(path, "amdgcn", "bitcode");
144  pathRef = StringRef(path.data(), path.size());
145 
146  // Fail if the path is invalid.
147  if (!llvm::sys::fs::is_directory(pathRef)) {
148  getOperation().emitError() << "ROCm amdgcn bitcode path: " << pathRef
149  << " does not exist or is not a directory";
150  return failure();
151  }
152 
153  // Get the ISA version.
154  StringRef isaVersion =
155  llvm::AMDGPU::getArchNameAMDGCN(llvm::AMDGPU::parseArchAMDGCN(chip));
156  isaVersion.consume_front("gfx");
157 
158  // Helper function for adding a library.
159  auto addLib = [&](const Twine &lib) -> bool {
160  auto baseSize = path.size();
161  llvm::sys::path::append(path, lib);
162  StringRef pathRef(path.data(), path.size());
163  if (!llvm::sys::fs::is_regular_file(pathRef)) {
164  getOperation().emitRemark() << "bitcode library path: " << pathRef
165  << " does not exist or is not a file";
166  return true;
167  }
168  fileList.push_back(pathRef.str());
169  path.truncate(baseSize);
170  return false;
171  };
172 
173  // Add ROCm device libraries. Fail if any of the libraries is not found, ie.
174  // if any of the `addLib` failed.
175  if ((any(libs & AMDGCNLibraries::Ocml) && addLib("ocml.bc")) ||
176  (any(libs & AMDGCNLibraries::Ockl) && addLib("ockl.bc")) ||
177  (any(libs & AMDGCNLibraries::Hip) && addLib("hip.bc")) ||
178  (any(libs & AMDGCNLibraries::OpenCL) && addLib("opencl.bc")) ||
179  (any(libs & (AMDGCNLibraries::Ocml | AMDGCNLibraries::Ockl)) &&
180  addLib("oclc_isa_version_" + isaVersion + ".bc")))
181  return failure();
182  return success();
183 }
184 
185 std::optional<SmallVector<std::unique_ptr<llvm::Module>>>
187  // Return if there are no libs to load.
188  if (deviceLibs == AMDGCNLibraries::None && fileList.empty())
190  if (failed(appendStandardLibs(deviceLibs)))
191  return std::nullopt;
193  if (failed(loadBitcodeFilesFromList(module.getContext(), fileList, bcFiles,
194  true)))
195  return std::nullopt;
196  return std::move(bcFiles);
197 }
198 
199 LogicalResult SerializeGPUModuleBase::handleBitcodeFile(llvm::Module &module) {
200  // Some ROCM builds don't strip this like they should
201  if (auto *openclVersion = module.getNamedMetadata("opencl.ocl.version"))
202  module.eraseNamedMetadata(openclVersion);
203  // Stop spamming us with clang version numbers
204  if (auto *ident = module.getNamedMetadata("llvm.ident"))
205  module.eraseNamedMetadata(ident);
206  // Override the libModules datalayout and target triple with the compiler's
207  // data layout should there be a discrepency.
209  return success();
210 }
211 
213  // If all libraries are not set, traverse the module to determine which
214  // libraries are required.
216  for (llvm::Function &f : module.functions()) {
217  if (f.hasExternalLinkage() && f.hasName() && !f.hasExactDefinition()) {
218  StringRef funcName = f.getName();
219  if ("printf" == funcName)
222  if (funcName.starts_with("__ockl_"))
224  if (funcName.starts_with("__ocml_"))
226  if (funcName == "__atomic_work_item_fence")
228  }
229  }
230  }
231  addControlVariables(module, deviceLibs, target.hasWave64(), target.hasDaz(),
232  target.hasFiniteOnly(), target.hasUnsafeMath(),
233  target.hasFastMath(), target.hasCorrectSqrt(),
234  target.getAbi());
235 }
236 
238  llvm::Module &module, AMDGCNLibraries libs, bool wave64, bool daz,
239  bool finiteOnly, bool unsafeMath, bool fastMath, bool correctSqrt,
240  StringRef abiVer) {
241  // Return if no device libraries are required.
242  if (libs == AMDGCNLibraries::None)
243  return;
244  // Helper function for adding control variables.
245  auto addControlVariable = [&module](StringRef name, uint32_t value,
246  uint32_t bitwidth) {
247  if (module.getNamedGlobal(name))
248  return;
249  llvm::IntegerType *type =
250  llvm::IntegerType::getIntNTy(module.getContext(), bitwidth);
251  llvm::GlobalVariable *controlVariable = new llvm::GlobalVariable(
252  module, /*isConstant=*/type, true,
253  llvm::GlobalValue::LinkageTypes::LinkOnceODRLinkage,
254  llvm::ConstantInt::get(type, value), name, /*before=*/nullptr,
255  /*threadLocalMode=*/llvm::GlobalValue::ThreadLocalMode::NotThreadLocal,
256  /*addressSpace=*/4);
257  controlVariable->setVisibility(
258  llvm::GlobalValue::VisibilityTypes::ProtectedVisibility);
259  controlVariable->setAlignment(llvm::MaybeAlign(bitwidth / 8));
260  controlVariable->setUnnamedAddr(llvm::GlobalValue::UnnamedAddr::Local);
261  };
262  // Add ocml related control variables.
263  if (any(libs & AMDGCNLibraries::Ocml)) {
264  addControlVariable("__oclc_finite_only_opt", finiteOnly || fastMath, 8);
265  addControlVariable("__oclc_daz_opt", daz || fastMath, 8);
266  addControlVariable("__oclc_correctly_rounded_sqrt32",
267  correctSqrt && !fastMath, 8);
268  addControlVariable("__oclc_unsafe_math_opt", unsafeMath || fastMath, 8);
269  }
270  // Add ocml or ockl related control variables.
271  if (any(libs & (AMDGCNLibraries::Ocml | AMDGCNLibraries::Ockl))) {
272  addControlVariable("__oclc_wavefrontsize64", wave64, 8);
273  int abi = 500;
274  abiVer.getAsInteger(0, abi);
275  addControlVariable("__oclc_ABI_version", abi, 32);
276  }
277 }
278 
279 std::optional<SmallVector<char, 0>>
281  auto loc = getOperation().getLoc();
282 
283  StringRef targetTriple = this->triple;
284 
285  SmallVector<char, 0> result;
286  llvm::raw_svector_ostream os(result);
287 
288  llvm::Triple triple(llvm::Triple::normalize(targetTriple));
289  std::string error;
290  const llvm::Target *target =
291  llvm::TargetRegistry::lookupTarget(triple.normalize(), error);
292  if (!target) {
293  emitError(loc, Twine("failed to lookup target: ") + error);
294  return std::nullopt;
295  }
296 
297  llvm::SourceMgr srcMgr;
298  srcMgr.AddNewSourceBuffer(llvm::MemoryBuffer::getMemBuffer(isa), SMLoc());
299 
300  const llvm::MCTargetOptions mcOptions;
301  std::unique_ptr<llvm::MCRegisterInfo> mri(
302  target->createMCRegInfo(targetTriple));
303  std::unique_ptr<llvm::MCAsmInfo> mai(
304  target->createMCAsmInfo(*mri, targetTriple, mcOptions));
305  std::unique_ptr<llvm::MCSubtargetInfo> sti(
306  target->createMCSubtargetInfo(targetTriple, chip, features));
307 
308  llvm::MCContext ctx(triple, mai.get(), mri.get(), sti.get(), &srcMgr,
309  &mcOptions);
310  std::unique_ptr<llvm::MCObjectFileInfo> mofi(target->createMCObjectFileInfo(
311  ctx, /*PIC=*/false, /*LargeCodeModel=*/false));
312  ctx.setObjectFileInfo(mofi.get());
313 
314  SmallString<128> cwd;
315  if (!llvm::sys::fs::current_path(cwd))
316  ctx.setCompilationDir(cwd);
317 
318  std::unique_ptr<llvm::MCStreamer> mcStreamer;
319  std::unique_ptr<llvm::MCInstrInfo> mcii(target->createMCInstrInfo());
320 
321  llvm::MCCodeEmitter *ce = target->createMCCodeEmitter(*mcii, ctx);
322  llvm::MCAsmBackend *mab = target->createMCAsmBackend(*sti, *mri, mcOptions);
323  mcStreamer.reset(target->createMCObjectStreamer(
324  triple, ctx, std::unique_ptr<llvm::MCAsmBackend>(mab),
325  mab->createObjectWriter(os), std::unique_ptr<llvm::MCCodeEmitter>(ce),
326  *sti, mcOptions.MCRelaxAll, mcOptions.MCIncrementalLinkerCompatible,
327  /*DWARFMustBeAtTheEnd*/ false));
328 
329  std::unique_ptr<llvm::MCAsmParser> parser(
330  createMCAsmParser(srcMgr, ctx, *mcStreamer, *mai));
331  std::unique_ptr<llvm::MCTargetAsmParser> tap(
332  target->createMCAsmParser(*sti, *parser, *mcii, mcOptions));
333 
334  if (!tap) {
335  emitError(loc, "assembler initialization error");
336  return std::nullopt;
337  }
338 
339  parser->setTargetParser(*tap);
340  parser->Run(false);
341  return std::move(result);
342 }
343 
344 std::optional<SmallVector<char, 0>>
345 SerializeGPUModuleBase::compileToBinary(const std::string &serializedISA) {
346  // Assemble the ISA.
347  std::optional<SmallVector<char, 0>> isaBinary = assembleIsa(serializedISA);
348 
349  if (!isaBinary) {
350  getOperation().emitError() << "failed during ISA assembling";
351  return std::nullopt;
352  }
353 
354  // Save the ISA binary to a temp file.
355  int tempIsaBinaryFd = -1;
356  SmallString<128> tempIsaBinaryFilename;
357  if (llvm::sys::fs::createTemporaryFile("kernel%%", "o", tempIsaBinaryFd,
358  tempIsaBinaryFilename)) {
360  << "failed to create a temporary file for dumping the ISA binary";
361  return std::nullopt;
362  }
363  llvm::FileRemover cleanupIsaBinary(tempIsaBinaryFilename);
364  {
365  llvm::raw_fd_ostream tempIsaBinaryOs(tempIsaBinaryFd, true);
366  tempIsaBinaryOs << StringRef(isaBinary->data(), isaBinary->size());
367  tempIsaBinaryOs.flush();
368  }
369 
370  // Create a temp file for HSA code object.
371  SmallString<128> tempHsacoFilename;
372  if (llvm::sys::fs::createTemporaryFile("kernel", "hsaco",
373  tempHsacoFilename)) {
375  << "failed to create a temporary file for the HSA code object";
376  return std::nullopt;
377  }
378  llvm::FileRemover cleanupHsaco(tempHsacoFilename);
379 
381  llvm::sys::path::append(lldPath, "llvm", "bin", "ld.lld");
382  int lldResult = llvm::sys::ExecuteAndWait(
383  lldPath,
384  {"ld.lld", "-shared", tempIsaBinaryFilename, "-o", tempHsacoFilename});
385  if (lldResult != 0) {
386  getOperation().emitError() << "lld invocation failed";
387  return std::nullopt;
388  }
389 
390  // Load the HSA code object.
391  auto hsacoFile =
392  llvm::MemoryBuffer::getFile(tempHsacoFilename, /*IsText=*/false);
393  if (!hsacoFile) {
395  << "failed to read the HSA code object from the temp file";
396  return std::nullopt;
397  }
398 
399  StringRef buffer = (*hsacoFile)->getBuffer();
400 
401  return SmallVector<char, 0>(buffer.begin(), buffer.end());
402 }
403 
404 std::optional<SmallVector<char, 0>> SerializeGPUModuleBase::moduleToObjectImpl(
405  const gpu::TargetOptions &targetOptions, llvm::Module &llvmModule) {
406  // Return LLVM IR if the compilation target is offload.
407 #define DEBUG_TYPE "serialize-to-llvm"
408  LLVM_DEBUG({
409  llvm::dbgs() << "LLVM IR for module: "
410  << cast<gpu::GPUModuleOp>(getOperation()).getNameAttr() << "\n"
411  << llvmModule << "\n";
412  });
413 #undef DEBUG_TYPE
414  if (targetOptions.getCompilationTarget() == gpu::CompilationTarget::Offload)
415  return SerializeGPUModuleBase::moduleToObject(llvmModule);
416 
417  std::optional<llvm::TargetMachine *> targetMachine =
419  if (!targetMachine) {
420  getOperation().emitError() << "target Machine unavailable for triple "
421  << triple << ", can't compile with LLVM";
422  return std::nullopt;
423  }
424 
425  // Translate the Module to ISA.
426  std::optional<std::string> serializedISA =
427  translateToISA(llvmModule, **targetMachine);
428  if (!serializedISA) {
429  getOperation().emitError() << "failed translating the module to ISA";
430  return std::nullopt;
431  }
432 #define DEBUG_TYPE "serialize-to-isa"
433  LLVM_DEBUG({
434  llvm::dbgs() << "ISA for module: "
435  << cast<gpu::GPUModuleOp>(getOperation()).getNameAttr() << "\n"
436  << *serializedISA << "\n";
437  });
438 #undef DEBUG_TYPE
439  // Return ISA assembly code if the compilation target is assembly.
440  if (targetOptions.getCompilationTarget() == gpu::CompilationTarget::Assembly)
441  return SmallVector<char, 0>(serializedISA->begin(), serializedISA->end());
442 
443  // Compiling to binary requires a valid ROCm path, fail if it's not found.
444  if (getToolkitPath().empty()) {
445  getOperation().emitError() << "invalid ROCm path, please set a valid path";
446  return std::nullopt;
447  }
448 
449  // Compile to binary.
450  return compileToBinary(*serializedISA);
451 }
452 
453 #if MLIR_ENABLE_ROCM_CONVERSIONS
454 namespace {
455 class AMDGPUSerializer : public SerializeGPUModuleBase {
456 public:
457  AMDGPUSerializer(Operation &module, ROCDLTargetAttr target,
458  const gpu::TargetOptions &targetOptions);
459 
460  std::optional<SmallVector<char, 0>>
461  moduleToObject(llvm::Module &llvmModule) override;
462 
463 private:
464  // Target options.
465  gpu::TargetOptions targetOptions;
466 };
467 } // namespace
468 
469 AMDGPUSerializer::AMDGPUSerializer(Operation &module, ROCDLTargetAttr target,
470  const gpu::TargetOptions &targetOptions)
471  : SerializeGPUModuleBase(module, target, targetOptions),
472  targetOptions(targetOptions) {}
473 
474 std::optional<SmallVector<char, 0>>
475 AMDGPUSerializer::moduleToObject(llvm::Module &llvmModule) {
476  return moduleToObjectImpl(targetOptions, llvmModule);
477 }
478 #endif // MLIR_ENABLE_ROCM_CONVERSIONS
479 
480 std::optional<SmallVector<char, 0>> ROCDLTargetAttrImpl::serializeToObject(
481  Attribute attribute, Operation *module,
482  const gpu::TargetOptions &options) const {
483  assert(module && "The module must be non null.");
484  if (!module)
485  return std::nullopt;
486  if (!mlir::isa<gpu::GPUModuleOp>(module)) {
487  module->emitError("module must be a GPU module");
488  return std::nullopt;
489  }
490 #if MLIR_ENABLE_ROCM_CONVERSIONS
491  AMDGPUSerializer serializer(*module, cast<ROCDLTargetAttr>(attribute),
492  options);
493  serializer.init();
494  return serializer.run();
495 #else
496  module->emitError("the `AMDGPU` target was not built. Please enable it when "
497  "building LLVM");
498  return std::nullopt;
499 #endif // MLIR_ENABLE_ROCM_CONVERSIONS
500 }
501 
502 Attribute
503 ROCDLTargetAttrImpl::createObject(Attribute attribute,
504  const SmallVector<char, 0> &object,
505  const gpu::TargetOptions &options) const {
506  gpu::CompilationTarget format = options.getCompilationTarget();
507  // If format is `fatbin` transform it to binary as `fatbin` is not yet
508  // supported.
509  if (format > gpu::CompilationTarget::Binary)
510  format = gpu::CompilationTarget::Binary;
511 
512  DictionaryAttr properties{};
513  Builder builder(attribute.getContext());
514  return builder.getAttr<gpu::ObjectAttr>(
515  attribute, format,
516  builder.getStringAttr(StringRef(object.data(), object.size())),
517  properties);
518 }
#define __DEFAULT_ROCM_PATH__
Definition: Target.cpp:50
static llvm::ManagedStatic< PassManagerOptions > options
Attributes are known-constant values of operations.
Definition: Attributes.h:25
MLIRContext * getContext() const
Return the context this attribute belongs to.
Definition: Attributes.cpp:37
This class is a general helper class for creating context-global objects like types,...
Definition: Builders.h:50
The DialectRegistry maps a dialect namespace to a constructor for the matching dialect.
void addExtension(std::unique_ptr< DialectExtensionBase > extension)
Add the given extension to the registry.
StringRef features
Target features.
static std::optional< std::string > translateToISA(llvm::Module &llvmModule, llvm::TargetMachine &targetMachine)
Utility function for translating to ISA, returns std::nullopt on failure.
virtual std::optional< SmallVector< char, 0 > > moduleToObject(llvm::Module &llvmModule)
Serializes the LLVM IR bitcode to an object file, by default it serializes to LLVM bitcode.
virtual void setDataLayoutAndTriple(llvm::Module &module)
Hook for computing the Datalayout.
StringRef triple
Target triple.
std::optional< llvm::TargetMachine * > getOrCreateTargetMachine()
Create the target machine based on the target triple and chip.
Operation & getOperation()
Returns the operation being serialized.
LogicalResult loadBitcodeFilesFromList(llvm::LLVMContext &context, ArrayRef< std::string > fileList, SmallVector< std::unique_ptr< llvm::Module >> &llvmModules, bool failureOnError=true)
Loads multiple bitcode files.
StringRef chip
Target chip.
Operation & module
Module to transform to a binary object.
MLIRContext is the top-level object for a collection of MLIR operations.
Definition: MLIRContext.h:60
void appendDialectRegistry(const DialectRegistry &registry)
Append the contents of the given dialect registry to the registry associated with this context.
Operation is the basic unit of execution within MLIR.
Definition: Operation.h:88
MLIRContext * getContext()
Return the context this operation is associated with.
Definition: Operation.h:216
Location getLoc()
The source location the operation was defined or derived from.
Definition: Operation.h:223
InFlightDiagnostic emitError(const Twine &message={})
Emit an error about fatal conditions with this operation, reporting up to any diagnostic handlers tha...
Definition: Operation.cpp:268
InFlightDiagnostic emitRemark(const Twine &message={})
Emit a remark about this operation, reporting up to any diagnostic handlers that may be listening.
Definition: Operation.cpp:289
Base class for all ROCDL serializations from GPU modules into binary strings.
Definition: Utils.h:46
ROCDLTargetAttr getTarget() const
Returns the target attribute.
Definition: Target.cpp:127
ArrayRef< std::string > getFileList() const
Returns the bitcode files to be loaded.
Definition: Target.cpp:131
AMDGCNLibraries deviceLibs
AMD GCN libraries to use when linking, the default is using none.
Definition: Utils.h:108
ROCDLTargetAttr target
ROCDL target attribute.
Definition: Utils.h:99
SerializeGPUModuleBase(Operation &module, ROCDLTargetAttr target, const gpu::TargetOptions &targetOptions={})
Initializes the toolkitPath with the path in targetOptions or if empty with the path in getROCMPath.
Definition: Target.cpp:94
std::optional< SmallVector< char, 0 > > moduleToObjectImpl(const gpu::TargetOptions &targetOptions, llvm::Module &llvmModule)
Default implementation of ModuleToObject::moduleToObject.
Definition: Target.cpp:404
virtual std::optional< SmallVector< std::unique_ptr< llvm::Module > > > loadBitcodeFiles(llvm::Module &module) override
Loads the bitcode files in fileList.
Definition: Target.cpp:186
void addControlVariables(llvm::Module &module, AMDGCNLibraries libs, bool wave64, bool daz, bool finiteOnly, bool unsafeMath, bool fastMath, bool correctSqrt, StringRef abiVer)
Adds oclc control variables to the LLVM module.
Definition: Target.cpp:237
std::optional< SmallVector< char, 0 > > assembleIsa(StringRef isa)
Returns the assembled ISA.
Definition: Target.cpp:280
SmallVector< std::string > fileList
List of LLVM bitcode files to link to.
Definition: Utils.h:105
std::string toolkitPath
ROCM toolkit path.
Definition: Utils.h:102
static void init()
Initializes the LLVM AMDGPU target by safely calling LLVMInitializeAMDGPU* methods if available.
Definition: Target.cpp:113
StringRef getToolkitPath() const
Returns the ROCM toolkit path.
Definition: Target.cpp:129
LogicalResult appendStandardLibs(AMDGCNLibraries libs)
Appends standard ROCm device libraries to fileList.
Definition: Target.cpp:135
LogicalResult handleBitcodeFile(llvm::Module &module) override
Removes unnecessary metadata from the loaded bitcode files.
Definition: Target.cpp:199
virtual std::optional< SmallVector< char, 0 > > compileToBinary(const std::string &serializedISA)
Compiles assembly to a binary.
Definition: Target.cpp:345
void handleModulePreLink(llvm::Module &module) override
Adds oclc control variables to the LLVM module.
Definition: Target.cpp:212
This class serves as an opaque interface for passing options to the TargetAttrInterface methods.
CompilationTarget getCompilationTarget() const
Returns the compilation target.
void registerROCDLTargetInterfaceExternalModels(DialectRegistry &registry)
Registers the TargetAttrInterface for the #rocdl.target attribute in the given registry.
Definition: Target.cpp:69
AMDGCNLibraries
Helper enum for specifying the AMD GCN device libraries required for compilation.
Definition: Utils.h:33
StringRef getROCMPath()
Searches & returns the path ROCM toolkit path, the search order is:
Definition: Target.cpp:84
Include the generated interface declarations.
InFlightDiagnostic emitError(Location loc)
Utility method to emit an error message using this location.
auto get(MLIRContext *context, Ts &&...params)
Helper method that injects context only if needed, this helps unify some of the attribute constructio...