MLIR
19.0.0git
|
#include "mlir/Dialect/Affine/IR/AffineOps.h"
#include "mlir/Dialect/Arith/IR/Arith.h"
#include "mlir/Dialect/Arith/Transforms/NarrowTypeEmulationConverter.h"
#include "mlir/Dialect/Arith/Utils/Utils.h"
#include "mlir/Dialect/MemRef/IR/MemRef.h"
#include "mlir/Dialect/MemRef/Utils/MemRefUtils.h"
#include "mlir/Dialect/Vector/IR/VectorOps.h"
#include "mlir/Dialect/Vector/Transforms/VectorRewritePatterns.h"
#include "mlir/IR/BuiltinAttributes.h"
#include "mlir/IR/BuiltinTypes.h"
#include "mlir/IR/TypeUtilities.h"
#include "mlir/IR/Value.h"
#include "mlir/Transforms/DialectConversion.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
#include <cstdint>
Go to the source code of this file.
Macros | |
#define | DEBUG_TYPE "vector-narrow-type-emulation" |
#define | DBGS() (llvm::dbgs() << "[" DEBUG_TYPE "]: ") |
#define | DBGSNL() (llvm::dbgs() << "\n") |
#define | LDBG(X) LLVM_DEBUG(DBGS() << X << "\n") |
Functions | |
static FailureOr< Operation * > | getCompressedMaskOp (OpBuilder &rewriter, Location loc, Value mask, int origElements, int scale) |
Returns a compressed mask. More... | |
static raw_ostream & | operator<< (raw_ostream &os, const SmallVector< SourceElementRangeList > &vec) |
static LogicalResult | commonConversionPrecondition (PatternRewriter &rewriter, VectorType preconditionType, Operation *op) |
Verify that the precondition type meets the common preconditions for any conversion. More... | |
static LogicalResult | alignedConversionPrecondition (PatternRewriter &rewriter, VectorType srcType, VectorType dstType, Operation *op) |
Verify that source and destination element types meet the precondition for the supported aligned conversion cases. More... | |
static Value | rewriteI4ToI8SignedExt (PatternRewriter &rewriter, Location loc, Value srcValue) |
Rewrite the i4 -> i8 signed extension into a sequence of shuffles and bitwise ops that take advantage of high-level information to avoid leaving LLVM to scramble with peephole optimizations. More... | |
static Value | rewriteI4ToI8UnsignedExt (PatternRewriter &rewriter, Location loc, Value srcValue) |
Rewrite the i4 -> i8 unsigned extension into a sequence of shuffles and bitwise ops that take advantage of high-level information to avoid leaving LLVM to scramble with peephole optimizations. More... | |
static Value | rewriteI8ToI4Trunc (PatternRewriter &rewriter, Location loc, Value srcValue) |
Rewrite the i8 -> i4 truncation into a sequence of shuffles and bitwise ops that take advantage of high-level information to avoid leaving LLVM to scramble with peephole optimizations. More... | |
#define DBGS | ( | ) | (llvm::dbgs() << "[" DEBUG_TYPE "]: ") |
Definition at line 31 of file VectorEmulateNarrowType.cpp.
#define DBGSNL | ( | ) | (llvm::dbgs() << "\n") |
Definition at line 32 of file VectorEmulateNarrowType.cpp.
#define DEBUG_TYPE "vector-narrow-type-emulation" |
Definition at line 30 of file VectorEmulateNarrowType.cpp.
#define LDBG | ( | X | ) | LLVM_DEBUG(DBGS() << X << "\n") |
Definition at line 33 of file VectorEmulateNarrowType.cpp.
|
static |
Verify that source and destination element types meet the precondition for the supported aligned conversion cases.
Alignment means that the either the source element type is multiple of the destination element type or the other way around.
NOTE: This method assumes that common conversion preconditions are met.
Definition at line 757 of file VectorEmulateNarrowType.cpp.
|
static |
Verify that the precondition type meets the common preconditions for any conversion.
Definition at line 724 of file VectorEmulateNarrowType.cpp.
|
static |
Returns a compressed mask.
The mask value is set only if any mask is present in the scale range. E.g., if scale
equals to 2, the following mask:
mask = [1, 1, 1, 0, 0, 0]
will return the following new compressed mask:
mask = [1, 1, 0]
Definition at line 43 of file VectorEmulateNarrowType.cpp.
References mlir::bindSymbols(), mlir::OpBuilder::create(), mlir::failure(), mlir::AffineExpr::floorDiv(), mlir::get(), mlir::Builder::getArrayAttr(), mlir::getAsOpFoldResult(), mlir::Builder::getContext(), mlir::Value::getDefiningOp(), mlir::Builder::getI1Type(), mlir::Builder::getI64IntegerAttr(), mlir::Operation::getResults(), mlir::Operation::getResultTypes(), mlir::getValueOrCreateConstantIndexOp(), and mlir::affine::makeComposedFoldedAffineApply().
|
static |
Definition at line 667 of file VectorEmulateNarrowType.cpp.
References mlir::detail::enumerate().
|
static |
Rewrite the i4 -> i8 signed extension into a sequence of shuffles and bitwise ops that take advantage of high-level information to avoid leaving LLVM to scramble with peephole optimizations.
Definition at line 857 of file VectorEmulateNarrowType.cpp.
References mlir::OpBuilder::create(), mlir::get(), mlir::Builder::getI8Type(), and mlir::Value::getType().
|
static |
Rewrite the i4 -> i8 unsigned extension into a sequence of shuffles and bitwise ops that take advantage of high-level information to avoid leaving LLVM to scramble with peephole optimizations.
Definition at line 886 of file VectorEmulateNarrowType.cpp.
References mlir::OpBuilder::create(), mlir::get(), mlir::Builder::getI8Type(), and mlir::Value::getType().
|
static |
Rewrite the i8 -> i4 truncation into a sequence of shuffles and bitwise ops that take advantage of high-level information to avoid leaving LLVM to scramble with peephole optimizations.
Definition at line 918 of file VectorEmulateNarrowType.cpp.
References mlir::OpBuilder::create(), mlir::get(), mlir::Builder::getI4Type(), mlir::Builder::getI64ArrayAttr(), and mlir::Value::getType().