MLIR
22.0.0git
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#include "mlir/Dialect/LLVMIR/NVVMDialect.h"
#include "mlir/Conversion/ConvertToLLVM/ToLLVMInterface.h"
#include "mlir/Dialect/GPU/IR/CompilationInterfaces.h"
#include "mlir/Dialect/GPU/IR/GPUDialect.h"
#include "mlir/IR/Builders.h"
#include "mlir/IR/BuiltinAttributes.h"
#include "mlir/IR/BuiltinTypes.h"
#include "mlir/IR/Diagnostics.h"
#include "mlir/IR/DialectImplementation.h"
#include "mlir/IR/MLIRContext.h"
#include "mlir/IR/Operation.h"
#include "mlir/IR/OperationSupport.h"
#include "mlir/IR/Types.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/TypeSwitch.h"
#include "llvm/IR/IRBuilder.h"
#include "llvm/Support/Casting.h"
#include "llvm/Support/FormatVariadic.h"
#include "llvm/Support/NVPTXAddrSpace.h"
#include "llvm/Support/raw_ostream.h"
#include <cassert>
#include <optional>
#include <string>
#include "mlir/Dialect/LLVMIR/NVVMOpsDialect.cpp.inc"
#include "mlir/Dialect/LLVMIR/NVVMOpsEnums.cpp.inc"
#include "mlir/Dialect/LLVMIR/NVVMOps.cpp.inc"
#include "mlir/Dialect/LLVMIR/NVVMOpsAttributes.cpp.inc"
Go to the source code of this file.
Macros | |
#define | CP_ASYNC_ID_IMPL(mod, size, suffix) llvm::Intrinsic::nvvm_cp_async_##mod##_shared_global_##size##suffix |
#define | GET_CP_ASYNC_ID(mod, size, has_cpsize) has_cpsize ? CP_ASYNC_ID_IMPL(mod, size, _s) : CP_ASYNC_ID_IMPL(mod, size, ) |
#define | CP_ASYNC_BULK_TENSOR_REDUCE_MODE(op, dim, mode) llvm::Intrinsic::nvvm_cp_async_bulk_tensor_##op##_##mode##_##dim##d |
#define | CP_ASYNC_BULK_TENSOR_REDUCE(op, dim, is_im2col) |
#define | GET_CP_ASYNC_BULK_TENSOR_ID(op, dims, is_im2col) |
#define | _none |
#define | CVT_F2TF32_ID_IMPL(rnd, relu, sf) |
#define | GET_CVT_F2TF32_ID(rnd, relu, sf) |
#define | GET_F32x2_TO_F6x2_ID(type, has_relu) |
#define | GET_F32x2_TO_F8X2_US_ID(rnd, has_satf) |
#define | GET_F32x2_TO_F8X2_S_ID(type, has_relu) |
#define | GET_F16x2_TO_F8X2_ID(type, has_relu) |
#define | GET_BF16X2_TO_F8X2_ID(rnd, has_satf) |
#define | TCGEN05_COMMIT_IMPL(cg, is_shared, mc) |
#define | GET_TCGEN05_COMMIT_ID(cta_group, is_shared, has_mc) |
#define | TCGEN05_CP_IMPL(shape_mc, src_fmt, cg) llvm::Intrinsic::nvvm_tcgen05_cp##shape_mc##src_fmt##cg |
#define | TCGEN05_CP_2CTA(shape_mc, src_fmt, is_2cta) |
#define | GET_TCGEN05_CP_ID(shape_mc, src_fmt, is_2cta) |
#define | GET_OP_LIST |
#define | GET_ATTRDEF_LIST |
#define | GET_OP_CLASSES |
#define | GET_ATTRDEF_CLASSES |
Functions | |
static LogicalResult | cpAsyncBulkTensorCommonVerifier (size_t tensorDims, bool isIm2Col, size_t numIm2ColOffsets, Location loc) |
static LogicalResult | verifyTMALoadParams (size_t tensorDims, size_t numIm2colOff, TMALoadMode mode, Location loc) |
static bool | isInt4PtxType (MMATypes type) |
static bool | isInt8PtxType (MMATypes type) |
static bool | isIntegerPtxType (MMATypes type) |
static std::pair< mlir::Type, unsigned > | inferMMATypeFromMNK (NVVM::MMATypes type, NVVM::MMAFrag frag, int m, int n, int k, MLIRContext *context) |
FailureOr< int > | getAllowedSizeK (NVVM::WGMMATypes typeA) |
LogicalResult | isAllowedWGMMADataType (NVVM::WGMMATypes typeD, NVVM::WGMMATypes typeA, NVVM::WGMMATypes typeB) |
LogicalResult | isAllowedSizeN (int sizeN, NVVM::WGMMATypes typeA) |
static llvm::Value * | packValInto64Bits (llvm::IRBuilderBase &builder, llvm::Value *result, llvm::Value *field, unsigned sizeInBits, unsigned start) |
Packs the given field into the result . More... | |
static unsigned | isValidVectorLength (NVVM::Tcgen05LdStShape shape, unsigned vecLen) |
static void | nvvmInferResultRanges (Operation *op, Value result, ArrayRef<::mlir::ConstantIntRanges > argRanges, SetIntRangeFn setResultRanges) |
Infer the result ranges for the NVVM SpecialRangeableRegisterOp that might have ConstantRangeAttr. More... | |
static llvm::Value * | getAsPackedI32 (llvm::Value *arg, llvm::IRBuilderBase &builder) |
static llvm::Value * | getParamCastedAddr (llvm::Value *addr, llvm::IRBuilderBase &builder) |
#define _none |
Definition at line 1686 of file NVVMDialect.cpp.
#define CP_ASYNC_BULK_TENSOR_REDUCE | ( | op, | |
dim, | |||
is_im2col | |||
) |
Definition at line 1640 of file NVVMDialect.cpp.
#define CP_ASYNC_BULK_TENSOR_REDUCE_MODE | ( | op, | |
dim, | |||
mode | |||
) | llvm::Intrinsic::nvvm_cp_async_bulk_tensor_##op##_##mode##_##dim##d |
Definition at line 1637 of file NVVMDialect.cpp.
#define CP_ASYNC_ID_IMPL | ( | mod, | |
size, | |||
suffix | |||
) | llvm::Intrinsic::nvvm_cp_async_##mod##_shared_global_##size##suffix |
Definition at line 1453 of file NVVMDialect.cpp.
#define CVT_F2TF32_ID_IMPL | ( | rnd, | |
relu, | |||
sf | |||
) |
Definition at line 1688 of file NVVMDialect.cpp.
#define GET_ATTRDEF_CLASSES |
Definition at line 2251 of file NVVMDialect.cpp.
#define GET_ATTRDEF_LIST |
#define GET_BF16X2_TO_F8X2_ID | ( | rnd, | |
has_satf | |||
) |
Definition at line 1774 of file NVVMDialect.cpp.
#define GET_CP_ASYNC_BULK_TENSOR_ID | ( | op, | |
dims, | |||
is_im2col | |||
) |
Definition at line 1644 of file NVVMDialect.cpp.
#define GET_CP_ASYNC_ID | ( | mod, | |
size, | |||
has_cpsize | |||
) | has_cpsize ? CP_ASYNC_ID_IMPL(mod, size, _s) : CP_ASYNC_ID_IMPL(mod, size, ) |
Definition at line 1456 of file NVVMDialect.cpp.
#define GET_CVT_F2TF32_ID | ( | rnd, | |
relu, | |||
sf | |||
) |
Definition at line 1692 of file NVVMDialect.cpp.
#define GET_F16x2_TO_F8X2_ID | ( | type, | |
has_relu | |||
) |
Definition at line 1758 of file NVVMDialect.cpp.
#define GET_F32x2_TO_F6x2_ID | ( | type, | |
has_relu | |||
) |
Definition at line 1713 of file NVVMDialect.cpp.
#define GET_F32x2_TO_F8X2_S_ID | ( | type, | |
has_relu | |||
) |
Definition at line 1732 of file NVVMDialect.cpp.
#define GET_F32x2_TO_F8X2_US_ID | ( | rnd, | |
has_satf | |||
) |
Definition at line 1728 of file NVVMDialect.cpp.
#define GET_OP_CLASSES |
Definition at line 2248 of file NVVMDialect.cpp.
#define GET_OP_LIST |
#define GET_TCGEN05_COMMIT_ID | ( | cta_group, | |
is_shared, | |||
has_mc | |||
) |
Definition at line 1837 of file NVVMDialect.cpp.
#define GET_TCGEN05_CP_ID | ( | shape_mc, | |
src_fmt, | |||
is_2cta | |||
) |
Definition at line 1871 of file NVVMDialect.cpp.
#define TCGEN05_COMMIT_IMPL | ( | cg, | |
is_shared, | |||
mc | |||
) |
Definition at line 1833 of file NVVMDialect.cpp.
#define TCGEN05_CP_2CTA | ( | shape_mc, | |
src_fmt, | |||
is_2cta | |||
) |
Definition at line 1867 of file NVVMDialect.cpp.
#define TCGEN05_CP_IMPL | ( | shape_mc, | |
src_fmt, | |||
cg | |||
) | llvm::Intrinsic::nvvm_tcgen05_cp##shape_mc##src_fmt##cg |
Definition at line 1864 of file NVVMDialect.cpp.
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Definition at line 55 of file NVVMDialect.cpp.
References mlir::emitError().
FailureOr<int> getAllowedSizeK | ( | NVVM::WGMMATypes | typeA | ) |
Definition at line 954 of file NVVMDialect.cpp.
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Definition at line 1959 of file NVVMDialect.cpp.
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Definition at line 2008 of file NVVMDialect.cpp.
References mlir::get().
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Definition at line 783 of file NVVMDialect.cpp.
References mlir::NVVM::inferMMAType().
LogicalResult isAllowedSizeN | ( | int | sizeN, |
NVVM::WGMMATypes | typeA | ||
) |
Definition at line 1010 of file NVVMDialect.cpp.
LogicalResult isAllowedWGMMADataType | ( | NVVM::WGMMATypes | typeD, |
NVVM::WGMMATypes | typeA, | ||
NVVM::WGMMATypes | typeB | ||
) |
Definition at line 968 of file NVVMDialect.cpp.
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Definition at line 303 of file NVVMDialect.cpp.
Referenced by isIntegerPtxType().
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Definition at line 307 of file NVVMDialect.cpp.
Referenced by isIntegerPtxType().
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Definition at line 311 of file NVVMDialect.cpp.
References isInt4PtxType(), and isInt8PtxType().
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Definition at line 1905 of file NVVMDialect.cpp.
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Infer the result ranges for the NVVM SpecialRangeableRegisterOp that might have ConstantRangeAttr.
Definition at line 1950 of file NVVMDialect.cpp.
References mlir::Operation::getAttrOfType().
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Packs the given field
into the result
.
The result
is 64-bits and each field
can be 32-bits or narrower.
Definition at line 1408 of file NVVMDialect.cpp.
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Definition at line 121 of file NVVMDialect.cpp.
References mlir::emitError().