30#define GEN_PASS_DEF_CONVERTVECTORTOLLVMPASS
31#include "mlir/Conversion/Passes.h.inc"
38struct ConvertVectorToLLVMPass
39 :
public impl::ConvertVectorToLLVMPassBase<ConvertVectorToLLVMPass> {
44 void getDependentDialects(DialectRegistry ®istry)
const override {
45 registry.
insert<LLVM::LLVMDialect>();
46 registry.
insert<arith::ArithDialect>();
47 registry.
insert<memref::MemRefDialect>();
48 registry.
insert<tensor::TensorDialect>();
50 registry.
insert<arm_neon::ArmNeonDialect>();
52 registry.
insert<arm_sve::ArmSVEDialect>();
54 registry.
insert<x86::X86Dialect>();
56 void runOnOperation()
override;
60void ConvertVectorToLLVMPass::runOnOperation() {
70 if (vectorContractLowering == vector::VectorContractLowering::LLVMIntr) {
80 if (vectorTransposeLowering == vector::VectorTransposeLowering::LLVMIntr) {
88 populateVectorMaskMaterializationPatterns(patterns,
89 force32BitVectorIndices);
90 populateVectorInsertExtractStridedSliceTransforms(patterns);
93 populateVectorFromElementsUnrollPatterns(patterns);
94 populateVectorToElementsUnrollPatterns(patterns);
111 const auto &dataLayoutAnalysis = getAnalysis<DataLayoutAnalysis>();
113 dataLayoutAnalysis.getAtOrAbove(getOperation()));
118 converter, patterns, reassociateFPReductions, force32BitVectorIndices,
119 useVectorAlignment, enableGEPInboundsNuw);
123 target.addLegalDialect<arith::ArithDialect>();
124 target.addLegalDialect<memref::MemRefDialect>();
125 target.addLegalOp<UnrealizedConversionCastOp>();
131 target.addLegalDialect<arm_neon::ArmNeonDialect>();
143 applyPartialConversion(getOperation(),
target, std::move(patterns))))
static llvm::ManagedStatic< PassManagerOptions > options
void populateLowerContractionToNeonI8MMPatterns(RewritePatternSet &patterns)
void populateLowerContractionToNeonBFMMLAPatterns(RewritePatternSet &patterns)
void populateLowerContractionToSVEBFMMLAPatterns(RewritePatternSet &patterns)
void populateLowerContractionToSVEI8MMPatterns(RewritePatternSet &patterns)
void populateVectorContractToMatrixMultiply(RewritePatternSet &patterns, PatternBenefit benefit=100)
Populate the pattern set with the following patterns:
void populateVectorRankReducingFMAPattern(RewritePatternSet &patterns)
Populates a pattern that rank-reduces n-D FMAs into (n-1)-D FMAs where n > 1.
void populateVectorShapeCastLoweringPatterns(RewritePatternSet &patterns, PatternBenefit benefit=1)
Populate the pattern set with the following patterns:
void populateVectorGatherLoweringPatterns(RewritePatternSet &patterns, PatternBenefit benefit=1)
Populate the pattern set with the following patterns:
void populateVectorTransferLoweringPatterns(RewritePatternSet &patterns, std::optional< unsigned > maxTransferRank=std::nullopt, PatternBenefit benefit=1)
Populate the pattern set with the following patterns:
void populateVectorTransposeLoweringPatterns(RewritePatternSet &patterns, VectorTransposeLowering vectorTransposeLowering, PatternBenefit benefit=1)
Populate the pattern set with the following patterns:
void populateVectorBroadcastLoweringPatterns(RewritePatternSet &patterns, PatternBenefit benefit=1)
Populate the pattern set with the following patterns:
void populateVectorBitCastLoweringPatterns(RewritePatternSet &patterns, int64_t targetRank=1, PatternBenefit benefit=1)
Populates the pattern set with the following patterns:
void populateVectorToVectorCanonicalizationPatterns(RewritePatternSet &patterns, PatternBenefit benefit=1)
Collect a set of vector-to-vector canonicalization patterns.
void populateVectorMaskOpLoweringPatterns(RewritePatternSet &patterns, PatternBenefit benefit=1)
Populate the pattern set with the following patterns:
void populateVectorTransposeToFlatTranspose(RewritePatternSet &patterns, PatternBenefit benefit=100)
Populate the pattern set with the following patterns:
void populateVectorInterleaveLoweringPatterns(RewritePatternSet &patterns, int64_t targetRank=1, PatternBenefit benefit=1)
Populate the pattern set with the following patterns:
void populateVectorContractLoweringPatterns(RewritePatternSet &patterns, VectorContractLowering vectorContractLoweringOption, PatternBenefit benefit=1, bool disableOuterProductLowering=false)
Populate the pattern set with the following patterns:
Include the generated interface declarations.
void configureArmSVELegalizeForExportTarget(LLVMConversionTarget &target)
Configure the target to support lowering ArmSVE ops to ops that map to LLVM intrinsics.
void populateVectorToLLVMConversionPatterns(const LLVMTypeConverter &converter, RewritePatternSet &patterns, bool reassociateFPReductions=false, bool force32BitVectorIndices=false, bool useVectorAlignment=false, bool enableGEPInboundsNuw=false)
Collect a set of patterns to convert from the Vector dialect to LLVM.
LogicalResult applyPatternsGreedily(Region ®ion, const FrozenRewritePatternSet &patterns, GreedyRewriteConfig config=GreedyRewriteConfig(), bool *changed=nullptr)
Rewrite ops in the given region, which must be isolated from above, by repeatedly applying the highes...
void configureX86LegalizeForExportTarget(LLVMConversionTarget &target)
Configure the target to support lowering X86 ops to ops that map to LLVM intrinsics.
void populateX86LegalizeForLLVMExportPatterns(LLVMTypeConverter &converter, RewritePatternSet &patterns)
Collect a set of patterns to lower X86 ops to ops that map to LLVM intrinsics.
void populateArmSVELegalizeForLLVMExportPatterns(const LLVMTypeConverter &converter, RewritePatternSet &patterns)
Collect a set of patterns to lower ArmSVE ops to ops that map to LLVM intrinsics.