MLIR 24.0.0git
ConvertVectorToLLVMPass.cpp
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1//===- VectorToLLVM.cpp - Conversion from Vector to the LLVM dialect ------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
10
26#include "mlir/Pass/Pass.h"
28
29namespace mlir {
30#define GEN_PASS_DEF_CONVERTVECTORTOLLVMPASS
31#include "mlir/Conversion/Passes.h.inc"
32} // namespace mlir
33
34using namespace mlir;
35using namespace mlir::vector;
36
37namespace {
38struct ConvertVectorToLLVMPass
39 : public impl::ConvertVectorToLLVMPassBase<ConvertVectorToLLVMPass> {
40
41 using Base::Base;
42
43 // Override explicitly to allow conditional dialect dependence.
44 void getDependentDialects(DialectRegistry &registry) const override {
45 registry.insert<LLVM::LLVMDialect>();
46 registry.insert<arith::ArithDialect>();
47 registry.insert<memref::MemRefDialect>();
48 registry.insert<tensor::TensorDialect>();
49 if (armNeon)
50 registry.insert<arm_neon::ArmNeonDialect>();
51 if (armSVE)
52 registry.insert<arm_sve::ArmSVEDialect>();
53 if (x86)
54 registry.insert<x86::X86Dialect>();
55 }
56 void runOnOperation() override;
57};
58} // namespace
59
60void ConvertVectorToLLVMPass::runOnOperation() {
61 // Perform progressive lowering of operations on slices and all contraction
62 // operations. Also materializes masks, lowers vector.step, rank-reduces FMA,
63 // applies folding and DCE.
64 {
65 RewritePatternSet patterns(&getContext());
69 populateVectorContractLoweringPatterns(patterns, vectorContractLowering);
70 if (vectorContractLowering == vector::VectorContractLowering::LLVMIntr) {
71 // This pattern creates a dependency on the LLVM dialect, hence we don't
72 // include it in `populateVectorContractLoweringPatterns` that is part of
73 // the Vector dialect (and should not depend on LLVM).
75 }
79 populateVectorTransposeLoweringPatterns(patterns, vectorTransposeLowering);
80 if (vectorTransposeLowering == vector::VectorTransposeLowering::LLVMIntr) {
81 // This pattern creates a dependency on the LLVM dialect, hence we don't
82 // include it in `populateVectorTransposeLoweringPatterns` that is part of
83 // the Vector dialect (and should not depend on LLVM).
85 }
86 // Vector transfer ops with rank > 1 should be lowered with VectorToSCF.
87 populateVectorTransferLoweringPatterns(patterns, /*maxTransferRank=*/1);
88 populateVectorMaskMaterializationPatterns(patterns,
89 force32BitVectorIndices);
90 populateVectorInsertExtractStridedSliceTransforms(patterns);
93 populateVectorFromElementsUnrollPatterns(patterns);
94 populateVectorToElementsUnrollPatterns(patterns);
95 if (armI8MM) {
96 if (armNeon)
98 if (armSVE)
100 }
101 if (armBF16) {
102 if (armNeon)
104 if (armSVE)
106 }
107 (void)applyPatternsGreedily(getOperation(), std::move(patterns));
108 }
109
110 // Convert to the LLVM IR dialect.
111 const auto &dataLayoutAnalysis = getAnalysis<DataLayoutAnalysis>();
112 LowerToLLVMOptions options(&getContext(),
113 dataLayoutAnalysis.getAtOrAbove(getOperation()));
114 LLVMTypeConverter converter(&getContext(), options, &dataLayoutAnalysis);
115 RewritePatternSet patterns(&getContext());
118 converter, patterns, reassociateFPReductions, force32BitVectorIndices,
119 useVectorAlignment, enableGEPInboundsNuw);
120
121 // Architecture specific augmentations.
122 LLVMConversionTarget target(getContext());
123 target.addLegalDialect<arith::ArithDialect>();
124 target.addLegalDialect<memref::MemRefDialect>();
125 target.addLegalOp<UnrealizedConversionCastOp>();
126
127 if (armNeon) {
128 // TODO: we may or may not want to include in-dialect lowering to
129 // LLVM-compatible operations here. So far, all operations in the dialect
130 // can be translated to LLVM IR so there is no conversion necessary.
131 target.addLegalDialect<arm_neon::ArmNeonDialect>();
132 }
133 if (armSVE) {
136 }
137 if (x86) {
139 populateX86LegalizeForLLVMExportPatterns(converter, patterns);
140 }
141
142 if (failed(
143 applyPartialConversion(getOperation(), target, std::move(patterns))))
144 signalPassFailure();
145}
b getContext())
static llvm::ManagedStatic< PassManagerOptions > options
void populateLowerContractionToNeonI8MMPatterns(RewritePatternSet &patterns)
void populateLowerContractionToNeonBFMMLAPatterns(RewritePatternSet &patterns)
void populateLowerContractionToSVEBFMMLAPatterns(RewritePatternSet &patterns)
void populateLowerContractionToSVEI8MMPatterns(RewritePatternSet &patterns)
detail::InFlightRemark failed(Location loc, RemarkOpts opts)
Report an optimization remark that failed.
Definition Remarks.h:733
void populateVectorContractToMatrixMultiply(RewritePatternSet &patterns, PatternBenefit benefit=100)
Populate the pattern set with the following patterns:
void populateVectorRankReducingFMAPattern(RewritePatternSet &patterns)
Populates a pattern that rank-reduces n-D FMAs into (n-1)-D FMAs where n > 1.
void populateVectorShapeCastLoweringPatterns(RewritePatternSet &patterns, PatternBenefit benefit=1)
Populate the pattern set with the following patterns:
void populateVectorGatherLoweringPatterns(RewritePatternSet &patterns, PatternBenefit benefit=1)
Populate the pattern set with the following patterns:
void populateVectorTransferLoweringPatterns(RewritePatternSet &patterns, std::optional< unsigned > maxTransferRank=std::nullopt, PatternBenefit benefit=1)
Populate the pattern set with the following patterns:
void populateVectorTransposeLoweringPatterns(RewritePatternSet &patterns, VectorTransposeLowering vectorTransposeLowering, PatternBenefit benefit=1)
Populate the pattern set with the following patterns:
void populateVectorBroadcastLoweringPatterns(RewritePatternSet &patterns, PatternBenefit benefit=1)
Populate the pattern set with the following patterns:
void populateVectorBitCastLoweringPatterns(RewritePatternSet &patterns, int64_t targetRank=1, PatternBenefit benefit=1)
Populates the pattern set with the following patterns:
void populateVectorToVectorCanonicalizationPatterns(RewritePatternSet &patterns, PatternBenefit benefit=1)
Collect a set of vector-to-vector canonicalization patterns.
void populateVectorMaskOpLoweringPatterns(RewritePatternSet &patterns, PatternBenefit benefit=1)
Populate the pattern set with the following patterns:
void populateVectorTransposeToFlatTranspose(RewritePatternSet &patterns, PatternBenefit benefit=100)
Populate the pattern set with the following patterns:
void populateVectorInterleaveLoweringPatterns(RewritePatternSet &patterns, int64_t targetRank=1, PatternBenefit benefit=1)
Populate the pattern set with the following patterns:
void populateVectorContractLoweringPatterns(RewritePatternSet &patterns, VectorContractLowering vectorContractLoweringOption, PatternBenefit benefit=1, bool disableOuterProductLowering=false)
Populate the pattern set with the following patterns:
Include the generated interface declarations.
void configureArmSVELegalizeForExportTarget(LLVMConversionTarget &target)
Configure the target to support lowering ArmSVE ops to ops that map to LLVM intrinsics.
void populateVectorToLLVMConversionPatterns(const LLVMTypeConverter &converter, RewritePatternSet &patterns, bool reassociateFPReductions=false, bool force32BitVectorIndices=false, bool useVectorAlignment=false, bool enableGEPInboundsNuw=false)
Collect a set of patterns to convert from the Vector dialect to LLVM.
LogicalResult applyPatternsGreedily(Region &region, const FrozenRewritePatternSet &patterns, GreedyRewriteConfig config=GreedyRewriteConfig(), bool *changed=nullptr)
Rewrite ops in the given region, which must be isolated from above, by repeatedly applying the highes...
void configureX86LegalizeForExportTarget(LLVMConversionTarget &target)
Configure the target to support lowering X86 ops to ops that map to LLVM intrinsics.
void populateX86LegalizeForLLVMExportPatterns(LLVMTypeConverter &converter, RewritePatternSet &patterns)
Collect a set of patterns to lower X86 ops to ops that map to LLVM intrinsics.
void populateArmSVELegalizeForLLVMExportPatterns(const LLVMTypeConverter &converter, RewritePatternSet &patterns)
Collect a set of patterns to lower ArmSVE ops to ops that map to LLVM intrinsics.