25#include "llvm/Support/DebugLog.h"
31#define GEN_PASS_DEF_CONVERTMATHTOROCDL
32#include "mlir/Conversion/Passes.h.inc"
37#define DEBUG_TYPE "math-to-rocdl"
39template <
typename OpTy>
42 StringRef f64Func, StringRef f16Func,
43 StringRef f32ApproxFunc =
"") {
46 f32ApproxFunc, f16Func);
55 ConversionPatternRewriter &rewriter)
const override {
57 Type opTy = op.getType();
60 if (
auto vectorType = dyn_cast<VectorType>(opTy))
61 opTy = vectorType.getElementType();
63 if (!isa<Float16Type, Float32Type>(opTy))
64 return rewriter.notifyMatchFailure(
65 op,
"fmed3 only supports f16 and f32 types");
68 if (
auto arrayType = dyn_cast<LLVM::LLVMArrayType>(resultType))
72 math::ClampFOp::Adaptor adaptor(operands);
73 return ROCDL::FMed3Op::create(rewriter, op.getLoc(), llvm1DVectorTy,
74 adaptor.getValue(), adaptor.getMin(),
80 rewriter.replaceOpWithNewOp<ROCDL::FMed3Op>(op, op.getType(), op.getValue(),
81 op.getMin(), op.getMax());
88 std::optional<amdgpu::Chipset> chipset) {
104 "__ocml_acos_f64",
"__ocml_acos_f16");
106 "__ocml_acosh_f64",
"__ocml_acosh_f16");
108 "__ocml_asin_f64",
"__ocml_asin_f16");
110 "__ocml_asinh_f64",
"__ocml_asinh_f16");
112 "__ocml_atan_f64",
"__ocml_atan_f16");
114 "__ocml_atanh_f64",
"__ocml_atanh_f16");
116 "__ocml_atan2_f64",
"__ocml_atan2_f16");
118 "__ocml_cbrt_f64",
"__ocml_cbrt_f16");
120 "__ocml_ceil_f64",
"__ocml_ceil_f16");
122 "__ocml_cos_f64",
"__ocml_cos_f16");
124 "__ocml_cosh_f64",
"__ocml_cosh_f16");
126 "__ocml_sinh_f64",
"__ocml_sinh_f16");
130 "__ocml_exp2_f64",
"__ocml_exp2_f16");
132 "__ocml_expm1_f64",
"__ocml_expm1_f16");
134 "__ocml_floor_f64",
"__ocml_floor_f16");
138 "__ocml_log10_f64",
"__ocml_log10_f16");
140 "__ocml_log1p_f64",
"__ocml_log1p_f16");
142 "__ocml_log2_f64",
"__ocml_log2_f16");
144 "__ocml_pow_f64",
"__ocml_pow_f16");
146 "__ocml_rsqrt_f64",
"__ocml_rsqrt_f16");
148 "__ocml_sin_f64",
"__ocml_sin_f16");
150 "__ocml_tanh_f64",
"__ocml_tanh_f16");
152 "__ocml_tan_f64",
"__ocml_tan_f16");
154 "__ocml_erf_f64",
"__ocml_erf_f16");
156 "__ocml_erfc_f64",
"__ocml_erfc_f16");
158 "__ocml_pown_f64",
"__ocml_pown_f16");
162 "__ocml_fmod_f64",
"__ocml_fmod_f16");
164 if (chipset.has_value() && chipset->majorVersion >= 9) {
167 LDBG() <<
"Chipset dependent patterns were not added";
172 : impl::ConvertMathToROCDLBase<ConvertMathToROCDLPass> {
173 using impl::ConvertMathToROCDLBase<
180 auto m = getOperation();
187 FailureOr<amdgpu::Chipset> maybeChipset;
188 if (!chipset.empty()) {
190 if (failed(maybeChipset))
191 return signalPassFailure();
195 succeeded(maybeChipset) ? std::optional(*maybeChipset) : std::nullopt);
199 .addLegalDialect<BuiltinDialect, func::FuncDialect, vector::VectorDialect,
200 LLVM::LLVMDialect, ROCDL::ROCDLDialect>();
201 target.addIllegalOp<LLVM::CosOp, LLVM::ExpOp, LLVM::Exp2Op, LLVM::FAbsOp,
202 LLVM::FCeilOp, LLVM::FFloorOp, LLVM::FRemOp, LLVM::LogOp,
203 LLVM::Log10Op, LLVM::Log2Op, LLVM::PowOp, LLVM::SinOp,
205 if (failed(applyPartialConversion(m,
target, std::move(patterns))))
static void populateOpPatterns(const LLVMTypeConverter &converter, RewritePatternSet &patterns, StringRef f32Func, StringRef f64Func, StringRef f16Func, StringRef f32ApproxFunc="")
static llvm::ManagedStatic< PassManagerOptions > options
ConvertOpToLLVMPattern(const LLVMTypeConverter &typeConverter, PatternBenefit benefit=1)
typename math::ClampFOp::Adaptor OpAdaptor
const LLVMTypeConverter * getTypeConverter() const
The main mechanism for performing data layout queries.
Conversion from types to the LLVM IR dialect.
Options to control the LLVM lowering.
MLIRContext is the top-level object for a collection of MLIR operations.
RewritePatternSet & add(ConstructorArg &&arg, ConstructorArgs &&...args)
Add an instance of each of the pattern types 'Ts' to the pattern list with the given arguments.
Instances of the Type class are uniqued, have an immutable identifier and an optional mutable compone...
This class provides an abstraction over the different types of ranges over Values.
This class represents an instance of an SSA value in the MLIR system, representing a computable value...
LogicalResult handleMultidimensionalVectors(Operation *op, ValueRange operands, const LLVMTypeConverter &typeConverter, std::function< Value(Type, ValueRange)> createOperand, ConversionPatternRewriter &rewriter)
Include the generated interface declarations.
void populateMathToROCDLConversionPatterns(const LLVMTypeConverter &converter, RewritePatternSet &patterns, std::optional< amdgpu::Chipset > chipset)
Populate the given list with patterns that convert from Math to ROCDL calls.
ConvertOpToLLVMPattern(const LLVMTypeConverter &typeConverter, PatternBenefit benefit=1)
LogicalResult matchAndRewrite(math::ClampFOp op, OpAdaptor adaptor, ConversionPatternRewriter &rewriter) const override
void runOnOperation() override
Rewriting that replaces SourceOp with a CallOp to f32Func or f64Func or f32ApproxFunc or f16Func or i...
Unrolls SourceOp to array/vector elements.
static FailureOr< Chipset > parse(StringRef name)
Parses the chipset version string and returns the chipset on success, and failure otherwise.