mlir.dialects._amdgpu_enum_gen¶

Attributes¶

_ods_ir

Classes¶

`AddressSpace`	AMDGPU-specific address spaces
`Scope`	AMDGPU-specific cache scopes. WGP - workgroup processor (CUs); SE - shader engine (GL2); DEV - device; SYS - system
`DPPPerm`	The possible permutations for a DPP operation
`LoadTemporalHint`	AMDGPU-specific prefetch temporal hints for load instructions. RT - regular temporal for both near and far caches; NT - non-temporal for both near and far caches; HT - high-priority temporal for both near and far caches; LU - last-use; NT_RT - non-temporal for near cache(s) and regular for far caches; RT_NT - regular for near cache(s) and non-temporal for far caches; NT_HT - non-temporal for near cache(s) and high-priority temporal for far caches
`MFMAPermB`	The possible permutations of the lanes storing B available in an MFMA
`sched_barrier_opt_enum`	The possible options for scheduling barriers

Functions¶

`register_attribute_builder`(kind[, replace, allow_existing])
`_amdgpu_addressspaceattr`(x, context)
`_amdgpu_cachescopeattr`(x, context)
`_amdgpu_dpppermattr`(x, context)
`_amdgpu_loadtemporalhintattr`(x, context)
`_amdgpu_mfmapermbattr`(x, context)
`_amdgpu_schedbarrieropoptattr`(x, context)

Module Contents¶

mlir.dialects._amdgpu_enum_gen.register_attribute_builder(kind, replace=False, allow_existing=False)¶

mlir.dialects._amdgpu_enum_gen._ods_ir¶

class mlir.dialects._amdgpu_enum_gen.AddressSpace¶

Bases: enum.IntEnum

AMDGPU-specific address spaces

FatRawBuffer = 0¶

BufferRsrc = 1¶

FatStructuredBuffer = 2¶

__str__()¶: Return str(self).

class mlir.dialects._amdgpu_enum_gen.Scope¶

Bases: enum.IntEnum

AMDGPU-specific cache scopes. WGP - workgroup processor (CUs); SE - shader engine (GL2); DEV - device; SYS - system

WGP = 0¶

SE = 1¶

DEV = 2¶

SYS = 3¶

__str__()¶: Return str(self).

class mlir.dialects._amdgpu_enum_gen.DPPPerm¶

Bases: enum.IntEnum

The possible permutations for a DPP operation

quad_perm = 0¶

row_shl = 1¶

row_shr = 2¶

row_ror = 3¶

wave_shl = 4¶

wave_shr = 5¶

wave_ror = 6¶

wave_rol = 7¶

row_mirror = 8¶

row_half_mirror = 9¶

row_bcast_15 = 10¶

row_bcast_31 = 11¶

__str__()¶: Return str(self).

class mlir.dialects._amdgpu_enum_gen.LoadTemporalHint¶

Bases: enum.IntEnum

AMDGPU-specific prefetch temporal hints for load instructions. RT - regular temporal for both near and far caches; NT - non-temporal for both near and far caches; HT - high-priority temporal for both near and far caches; LU - last-use; NT_RT - non-temporal for near cache(s) and regular for far caches; RT_NT - regular for near cache(s) and non-temporal for far caches; NT_HT - non-temporal for near cache(s) and high-priority temporal for far caches

RT = 0¶

NT = 1¶

HT = 2¶

LU = 3¶

NT_RT = 4¶

RT_NT = 5¶

NT_HT = 6¶

__str__()¶: Return str(self).

class mlir.dialects._amdgpu_enum_gen.MFMAPermB¶

Bases: enum.IntEnum

The possible permutations of the lanes storing B available in an MFMA

none = 0¶

bcast_first_32 = 1¶

bcast_second_32 = 2¶

rotate_16_right = 3¶

bcast_first_16 = 4¶

bcast_second_16 = 5¶

bcast_third_16 = 6¶

bcast_fourth_16 = 7¶

__str__()¶: Return str(self).

class mlir.dialects._amdgpu_enum_gen.sched_barrier_opt_enum¶

Bases: enum.IntFlag

The possible options for scheduling barriers

none = 0¶

non_mem_non_sideffect = 1¶

valu = 2¶

salu = 4¶

mfma_wmma = 8¶

all_vmem = 16¶

vmem_read = 32¶

vmem_write = 64¶

all_ds = 128¶

ds_read = 256¶

ds_write = 512¶

transcendental = 1024¶

__iter__()¶

__len__()¶

__str__()¶: Return str(self).

mlir.dialects._amdgpu_enum_gen._amdgpu_addressspaceattr(x, context)¶

mlir.dialects._amdgpu_enum_gen._amdgpu_cachescopeattr(x, context)¶

mlir.dialects._amdgpu_enum_gen._amdgpu_dpppermattr(x, context)¶

mlir.dialects._amdgpu_enum_gen._amdgpu_loadtemporalhintattr(x, context)¶

mlir.dialects._amdgpu_enum_gen._amdgpu_mfmapermbattr(x, context)¶

mlir.dialects._amdgpu_enum_gen._amdgpu_schedbarrieropoptattr(x, context)¶