mlir.dialects._amdgpu_enum_gen¶

Attributes¶

_ods_ir

Classes¶

`AddressSpace`	AMDGPU-specific address spaces
`Scope`	AMDGPU-specific cache scopes. WGP - workgroup processor (CUs); SE - shader engine (GL2); DEV - device; SYS - system
`DPPPerm`	The possible permutations for a DPP operation
`LoadTemporalHint`	AMDGPU-specific prefetch temporal hints for load instructions. RT - regular temporal for both near and far caches; NT - non-temporal for both near and far caches; HT - high-priority temporal for both near and far caches; LU - last-use; NT_RT - non-temporal for near cache(s) and regular for far caches; RT_NT - regular for near cache(s) and non-temporal for far caches; NT_HT - non-temporal for near cache(s) and high-priority temporal for far caches
`Gfx12AtomicCachePolicy`	gfx12 atomic cache policy bits
`Gfx12CachePolicy`	gfx12 cache policy bits
`Gfx942CachePolicy`	gfx942 buffer cache policy bits
`MFMANegModifier`	negation modifier bitfield for gfx94x double-precision MFMA
`MFMAPermB`	permutations of the lanes storing B in an MFMA
`MatrixFormat`	matrix operand formats selected by scaled MFMA/WMMA format fields
`PreGfx12CachePolicy`	pre-gfx12 buffer cache policy bits
`SchedGroupMask`	instruction type mask for scheduling barriers
`WMMACModifier`	WMMA C operand modifiers
`WMMAMatrixScale`	matrix scale row selector
`WMMAMatrixScaleFormat`	matrix scale exponent formats

Functions¶

`register_attribute_builder`(kind[, replace, allow_existing])
`_amdgpu_addressspaceattr`(x, context)
`_amdgpu_cachescopeattr`(x, context)
`_amdgpu_dpppermattr`(x, context)
`_amdgpu_loadtemporalhintattr`(x, context)

Module Contents¶

mlir.dialects._amdgpu_enum_gen.register_attribute_builder(kind, replace=False, allow_existing=False)¶

mlir.dialects._amdgpu_enum_gen._ods_ir¶

class mlir.dialects._amdgpu_enum_gen.AddressSpace¶

Bases: enum.IntEnum

AMDGPU-specific address spaces

FatRawBuffer = 0¶

BufferRsrc = 1¶

FatStructuredBuffer = 2¶

__str__()¶: Return str(self).

class mlir.dialects._amdgpu_enum_gen.Scope¶

Bases: enum.IntEnum

AMDGPU-specific cache scopes. WGP - workgroup processor (CUs); SE - shader engine (GL2); DEV - device; SYS - system

WGP = 0¶

SE = 1¶

DEV = 2¶

SYS = 3¶

__str__()¶: Return str(self).

class mlir.dialects._amdgpu_enum_gen.DPPPerm¶

Bases: enum.IntEnum

The possible permutations for a DPP operation

quad_perm = 0¶

row_shl = 1¶

row_shr = 2¶

row_ror = 3¶

wave_shl = 4¶

wave_shr = 5¶

wave_ror = 6¶

wave_rol = 7¶

row_mirror = 8¶

row_half_mirror = 9¶

row_bcast_15 = 10¶

row_bcast_31 = 11¶

__str__()¶: Return str(self).

class mlir.dialects._amdgpu_enum_gen.LoadTemporalHint¶

Bases: enum.IntEnum

AMDGPU-specific prefetch temporal hints for load instructions. RT - regular temporal for both near and far caches; NT - non-temporal for both near and far caches; HT - high-priority temporal for both near and far caches; LU - last-use; NT_RT - non-temporal for near cache(s) and regular for far caches; RT_NT - regular for near cache(s) and non-temporal for far caches; NT_HT - non-temporal for near cache(s) and high-priority temporal for far caches

RT = 0¶

NT = 1¶

HT = 2¶

LU = 3¶

NT_RT = 4¶

RT_NT = 5¶

NT_HT = 6¶

__str__()¶: Return str(self).

class mlir.dialects._amdgpu_enum_gen.Gfx12AtomicCachePolicy¶

Bases: enum.IntFlag

gfx12 atomic cache policy bits

none = 0¶

keep_return = 1¶

nt = 2¶

cascade = 4¶

scope_se = 8¶

scope_dev = 16¶

scope_sys = 24¶

nv = 32¶

volatile_op = 2147483648¶

__iter__()¶

__len__()¶

__str__()¶: Return str(self).

class mlir.dialects._amdgpu_enum_gen.Gfx12CachePolicy¶

Bases: enum.IntFlag

gfx12 cache policy bits

none = 0¶

nt = 1¶

ht = 2¶

lu = 3¶

nt_rt = 4¶

rt_nt = 5¶

nt_ht = 6¶

nt_wb = 7¶

scope_se = 8¶

scope_dev = 16¶

scope_sys = 24¶

nv = 32¶

swz = 64¶

scal = 2048¶

volatile_op = 2147483648¶

__iter__()¶

__len__()¶

__str__()¶: Return str(self).

class mlir.dialects._amdgpu_enum_gen.Gfx942CachePolicy¶

Bases: enum.IntFlag

gfx942 buffer cache policy bits

none = 0¶

sc0 = 1¶

nt = 2¶

swz = 8¶

sc1 = 16¶

volatile_op = 2147483648¶

__iter__()¶

__len__()¶

__str__()¶: Return str(self).

class mlir.dialects._amdgpu_enum_gen.MFMANegModifier¶

Bases: enum.IntFlag

negation modifier bitfield for gfx94x double-precision MFMA

none = 0¶

neg_a = 1¶

neg_b = 2¶

neg_c = 4¶

__iter__()¶

__len__()¶

__str__()¶: Return str(self).

class mlir.dialects._amdgpu_enum_gen.MFMAPermB¶

Bases: enum.IntEnum

permutations of the lanes storing B in an MFMA

none = 0¶

bcast_first_32 = 1¶

bcast_second_32 = 2¶

rotate_16_right = 3¶

bcast_first_16 = 4¶

bcast_second_16 = 5¶

bcast_third_16 = 6¶

bcast_fourth_16 = 7¶

__str__()¶: Return str(self).

class mlir.dialects._amdgpu_enum_gen.MatrixFormat¶

Bases: enum.IntEnum

matrix operand formats selected by scaled MFMA/WMMA format fields

fp8_e4m3 = 0¶

fp8_e5m2 = 1¶

fp6_e2m3 = 2¶

fp6_e3m2 = 3¶

fp4_e2m1 = 4¶

__str__()¶: Return str(self).

class mlir.dialects._amdgpu_enum_gen.PreGfx12CachePolicy¶

Bases: enum.IntFlag

pre-gfx12 buffer cache policy bits

none = 0¶

glc = 1¶

slc = 2¶

dlc = 4¶

swz = 8¶

scc = 16¶

all = 23¶

volatile_op = 2147483648¶

__iter__()¶

__len__()¶

__str__()¶: Return str(self).

class mlir.dialects._amdgpu_enum_gen.SchedGroupMask¶

Bases: enum.IntFlag

instruction type mask for scheduling barriers

none = 0¶

non_mem_non_sideeffect = 1¶

valu = 2¶

salu = 4¶

mfma_wmma = 8¶

all_vmem = 16¶

vmem_read = 32¶

vmem_write = 64¶

all_ds = 128¶

ds_read = 256¶

ds_write = 512¶

transcendental = 1024¶

ldsdma = 2048¶

all = 4095¶

__iter__()¶

__len__()¶

__str__()¶: Return str(self).

class mlir.dialects._amdgpu_enum_gen.WMMACModifier¶

Bases: enum.IntFlag

WMMA C operand modifiers

none = 0¶

neg = 1¶

abs = 2¶

neg_abs = 3¶

__iter__()¶

__len__()¶

__str__()¶: Return str(self).

class mlir.dialects._amdgpu_enum_gen.WMMAMatrixScale¶

Bases: enum.IntEnum

matrix scale row selector

row0 = 0¶

row1 = 1¶

__str__()¶: Return str(self).

class mlir.dialects._amdgpu_enum_gen.WMMAMatrixScaleFormat¶

Bases: enum.IntEnum

matrix scale exponent formats

e8 = 0¶

e5m3 = 1¶

e4m3 = 2¶

__str__()¶: Return str(self).

mlir.dialects._amdgpu_enum_gen._amdgpu_addressspaceattr(x, context)¶

mlir.dialects._amdgpu_enum_gen._amdgpu_cachescopeattr(x, context)¶

mlir.dialects._amdgpu_enum_gen._amdgpu_dpppermattr(x, context)¶

mlir.dialects._amdgpu_enum_gen._amdgpu_loadtemporalhintattr(x, context)¶