mlir.dialects._x86_ops_gen¶

Attributes¶

_ods_ir

Classes¶

`_Dialect`
`AVX10DotInt8Op`	The `dot` op is an AVX10-Int8 specific op that can lower to the proper
`AVX10DotInt8OpAdaptor`
`BcstToPackedF32Op`	From the Intel Intrinsics Guide:
`BcstToPackedF32OpAdaptor`
`CvtPackedEvenIndexedToF32Op`	From the Intel Intrinsics Guide:
`CvtPackedEvenIndexedToF32OpAdaptor`
`CvtPackedF32ToBF16Op`	The `convert_f32_to_bf16` op is an AVX512-BF16 specific op that can lower
`CvtPackedF32ToBF16OpAdaptor`
`CvtPackedOddIndexedToF32Op`	From the Intel Intrinsics Guide:
`CvtPackedOddIndexedToF32OpAdaptor`
`DotBF16Op`	The `dot` op is an AVX512-BF16 specific op that can lower to the proper
`DotBF16OpAdaptor`
`DotInt8Op`	The `dot` op is an AVX2-Int8 specific op that can lower to the proper
`DotInt8OpAdaptor`
`DotOp`	Computes the 4-way dot products of the lower and higher parts of the source
`DotOpAdaptor`
`MaskCompressOp`	The mask.compress op is an AVX512 specific op that can lower to the
`MaskCompressOpAdaptor`
`MaskRndScaleOp`	The mask.rndscale op is an AVX512 specific op that can lower to the proper
`MaskRndScaleOpAdaptor`
`MaskScaleFOp`	The `mask.scalef` op is an AVX512 specific op that can lower to the proper
`MaskScaleFOpAdaptor`
`RsqrtOp`
`RsqrtOpAdaptor`
`TileLoadOp`	Loads a tile from memory defined by a `base` and `indices`, with the
`TileLoadOpAdaptor`
`TileMulFOp`	Multiplies a "m x k" tile with a "k x n" tile and accumulates the results
`TileMulFOpAdaptor`
`TileMulIOp`	Multiplies a "m x k" tile with a "k x n" tile and accumulates the results
`TileMulIOpAdaptor`
`TileStoreOp`	Stores a tile to memory defined by a `base` and `indices`, with the
`TileStoreOpAdaptor`
`TileZeroOp`	Zeroes the destination tile, with the shape defined by the 2-dim
`TileZeroOpAdaptor`
`Vp2IntersectOp`	The `vp2intersect` op is an AVX512 specific op that can lower to the proper
`Vp2IntersectOpAdaptor`

Functions¶

`avx10_dot_i8`(→ _ods_ir)
`avx_bcst_to_f32_packed`(→ _ods_ir)
`avx_cvt_packed_even_indexed_to_f32`(→ _ods_ir)
`avx512_cvt_packed_f32_to_bf16`(→ _ods_ir)
`avx_cvt_packed_odd_indexed_to_f32`(→ _ods_ir)
`avx512_dot`(→ _ods_ir)
`avx_dot_i8`(→ _ods_ir)
`avx_intr_dot`(→ _ods_ir)
`avx512_mask_compress`(→ _ods_ir)
`avx512_mask_rndscale`(→ _ods_ir)
`avx512_mask_scalef`(→ _ods_ir)
`avx_rsqrt`(→ _ods_ir)
`amx_tile_load`(→ _ods_ir)
`amx_tile_mulf`(→ _ods_ir)
`amx_tile_muli`(→ _ods_ir)
`amx_tile_store`(→ TileStoreOp)
`amx_tile_zero`(→ _ods_ir)
`avx512_vp2intersect`(→ _ods_ir)

Module Contents¶

mlir.dialects._x86_ops_gen._ods_ir¶

class mlir.dialects._x86_ops_gen._Dialect(descriptor: object)¶

Bases: _ods_ir

DIALECT_NAMESPACE = 'x86'¶

class mlir.dialects._x86_ops_gen.AVX10DotInt8Op(w, a, b, *, results=None, loc=None, ip=None)¶

Bases: _ods_ir

The dot op is an AVX10-Int8 specific op that can lower to the proper LLVMAVX10-INT8 operation llvm.vpdpbssd.512.

Multiply groups of 4 adjacent pairs of signed 8-bit integers in a with corresponding signed 8-bit integers in b, producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in w, and store the packed 32-bit results in dst.

Example:

%dst = x86.avx10.dot.i8 %w, %a, %b : vector<64xi8> -> vector<16xi32>

OPERATION_NAME = 'x86.avx10.dot.i8'¶

_ODS_REGIONS = (0, True)¶

w() → _ods_ir[_ods_ir]¶

a() → _ods_ir[_ods_ir]¶

b() → _ods_ir[_ods_ir]¶

dst() → _ods_ir[_ods_ir]¶

class mlir.dialects._x86_ops_gen.AVX10DotInt8OpAdaptor(operands: list, attributes: OpAttributeMap)¶

class mlir.dialects._x86_ops_gen.AVX10DotInt8OpAdaptor(operands: list, opview: OpView)

Bases: _ods_ir

OPERATION_NAME = 'x86.avx10.dot.i8'¶

w() → _ods_ir[_ods_ir]¶

a() → _ods_ir[_ods_ir]¶

b() → _ods_ir[_ods_ir]¶

mlir.dialects._x86_ops_gen.avx10_dot_i8(w, a, b, *, results=None, loc=None, ip=None) → _ods_ir¶

class mlir.dialects._x86_ops_gen.BcstToPackedF32Op(dst, a, *, loc=None, ip=None)¶

Bases: _ods_ir

From the Intel Intrinsics Guide:¶

Convert scalar BF16 or F16 (16-bit) floating-point element stored at memory locations starting at location __A to a single-precision (32-bit) floating-point, broadcast it to packed single-precision (32-bit) floating-point elements, and store the results in dst.

Example:

%dst = x86.avx.bcst_to_f32.packed %a : memref<1xbf16> -> vector<8xf32>
%dst = x86.avx.bcst_to_f32.packed %a : memref<1xf16> -> vector<8xf32>

OPERATION_NAME = 'x86.avx.bcst_to_f32.packed'¶

_ODS_REGIONS = (0, True)¶

a() → _ods_ir[_ods_ir]¶

dst() → _ods_ir[_ods_ir]¶

class mlir.dialects._x86_ops_gen.BcstToPackedF32OpAdaptor(operands: list, attributes: OpAttributeMap)¶

class mlir.dialects._x86_ops_gen.BcstToPackedF32OpAdaptor(operands: list, opview: OpView)

Bases: _ods_ir

OPERATION_NAME = 'x86.avx.bcst_to_f32.packed'¶

a() → _ods_ir[_ods_ir]¶

mlir.dialects._x86_ops_gen.avx_bcst_to_f32_packed(dst, a, *, loc=None, ip=None) → _ods_ir¶

class mlir.dialects._x86_ops_gen.CvtPackedEvenIndexedToF32Op(dst, a, *, loc=None, ip=None)¶

Bases: _ods_ir

From the Intel Intrinsics Guide:¶

Convert packed BF16 or F16 (16-bit) floating-point even-indexed elements stored at memory locations starting at location __A to packed single-precision (32-bit) floating-point elements, and store the results in dst.

Example:

%dst = x86.avx.cvt.packed.even.indexed_to_f32 %a : memref<16xbf16> -> vector<8xf32>
%dst = x86.avx.cvt.packed.even.indexed_to_f32 %a : memref<16xf16> -> vector<8xf32>

OPERATION_NAME = 'x86.avx.cvt.packed.even.indexed_to_f32'¶

_ODS_REGIONS = (0, True)¶

a() → _ods_ir[_ods_ir]¶

dst() → _ods_ir[_ods_ir]¶

class mlir.dialects._x86_ops_gen.CvtPackedEvenIndexedToF32OpAdaptor(operands: list, attributes: OpAttributeMap)¶

class mlir.dialects._x86_ops_gen.CvtPackedEvenIndexedToF32OpAdaptor(operands: list, opview: OpView)

Bases: _ods_ir

OPERATION_NAME = 'x86.avx.cvt.packed.even.indexed_to_f32'¶

a() → _ods_ir[_ods_ir]¶

mlir.dialects._x86_ops_gen.avx_cvt_packed_even_indexed_to_f32(dst, a, *, loc=None, ip=None) → _ods_ir¶

class mlir.dialects._x86_ops_gen.CvtPackedF32ToBF16Op(dst, a, *, loc=None, ip=None)¶

Bases: _ods_ir

The convert_f32_to_bf16 op is an AVX512-BF16 specific op that can lower to the proper LLVMAVX512BF16 operation llvm.cvtneps2bf16 depending on the width of MLIR vectors it is applied to.

From the Intel Intrinsics Guide:¶

Convert packed single-precision (32-bit) floating-point elements in a to packed BF16 (16-bit) floating-point elements, and store the results in dst.

Example:

%dst = x86.avx512.cvt.packed.f32_to_bf16 %a : vector<8xf32> -> vector<8xbf16>

OPERATION_NAME = 'x86.avx512.cvt.packed.f32_to_bf16'¶

_ODS_REGIONS = (0, True)¶

a() → _ods_ir[_ods_ir]¶

dst() → _ods_ir[_ods_ir]¶

class mlir.dialects._x86_ops_gen.CvtPackedF32ToBF16OpAdaptor(operands: list, attributes: OpAttributeMap)¶

class mlir.dialects._x86_ops_gen.CvtPackedF32ToBF16OpAdaptor(operands: list, opview: OpView)

Bases: _ods_ir

OPERATION_NAME = 'x86.avx512.cvt.packed.f32_to_bf16'¶

a() → _ods_ir[_ods_ir]¶

mlir.dialects._x86_ops_gen.avx512_cvt_packed_f32_to_bf16(dst, a, *, loc=None, ip=None) → _ods_ir¶

class mlir.dialects._x86_ops_gen.CvtPackedOddIndexedToF32Op(dst, a, *, loc=None, ip=None)¶

Bases: _ods_ir

From the Intel Intrinsics Guide:¶

Convert packed BF16 or F16 (16-bit) floating-point odd-indexed elements stored at memory locations starting at location __A to packed single-precision (32-bit) floating-point elements, and store the results in dst.

Example:

%dst = x86.avx.cvt.packed.odd.indexed_to_f32 %a : memref<16xbf16> -> vector<8xf32>
%dst = x86.avx.cvt.packed.odd.indexed_to_f32 %a : memref<16xf16> -> vector<8xf32>

OPERATION_NAME = 'x86.avx.cvt.packed.odd.indexed_to_f32'¶

_ODS_REGIONS = (0, True)¶

a() → _ods_ir[_ods_ir]¶

dst() → _ods_ir[_ods_ir]¶

class mlir.dialects._x86_ops_gen.CvtPackedOddIndexedToF32OpAdaptor(operands: list, attributes: OpAttributeMap)¶

class mlir.dialects._x86_ops_gen.CvtPackedOddIndexedToF32OpAdaptor(operands: list, opview: OpView)

Bases: _ods_ir

OPERATION_NAME = 'x86.avx.cvt.packed.odd.indexed_to_f32'¶

a() → _ods_ir[_ods_ir]¶

mlir.dialects._x86_ops_gen.avx_cvt_packed_odd_indexed_to_f32(dst, a, *, loc=None, ip=None) → _ods_ir¶

class mlir.dialects._x86_ops_gen.DotBF16Op(src, a, b, *, results=None, loc=None, ip=None)¶

Bases: _ods_ir

The dot op is an AVX512-BF16 specific op that can lower to the proper LLVMAVX512BF16 operation llvm.dpbf16ps depending on the width of MLIR vectors it is applied to.

From the Intel Intrinsics Guide:¶

Compute dot-product of BF16 (16-bit) floating-point pairs in a and b, accumulating the intermediate single-precision (32-bit) floating-point elements with elements in src, and store the results in dst.

Example:

%dst = x86.avx512.dot %src, %a, %b : vector<32xbf16> -> vector<16xf32>

OPERATION_NAME = 'x86.avx512.dot'¶

_ODS_REGIONS = (0, True)¶

src() → _ods_ir[_ods_ir]¶

a() → _ods_ir[_ods_ir]¶

b() → _ods_ir[_ods_ir]¶

dst() → _ods_ir[_ods_ir]¶

class mlir.dialects._x86_ops_gen.DotBF16OpAdaptor(operands: list, attributes: OpAttributeMap)¶

class mlir.dialects._x86_ops_gen.DotBF16OpAdaptor(operands: list, opview: OpView)

Bases: _ods_ir

OPERATION_NAME = 'x86.avx512.dot'¶

src() → _ods_ir[_ods_ir]¶

a() → _ods_ir[_ods_ir]¶

b() → _ods_ir[_ods_ir]¶

mlir.dialects._x86_ops_gen.avx512_dot(src, a, b, *, results=None, loc=None, ip=None) → _ods_ir¶

class mlir.dialects._x86_ops_gen.DotInt8Op(w, a, b, *, results=None, loc=None, ip=None)¶

Bases: _ods_ir

The dot op is an AVX2-Int8 specific op that can lower to the proper LLVMAVX2-INT8 operation llvm.vpdpbssd depending on the width of MLIR vectors it is applied to.

From the Intel Intrinsics Guide:¶

Example:

%dst = x86.avx.dot.i8 %w, %a, %b : vector<32xi8> -> vector<8xi32>

OPERATION_NAME = 'x86.avx.dot.i8'¶

_ODS_REGIONS = (0, True)¶

w() → _ods_ir[_ods_ir]¶

a() → _ods_ir[_ods_ir]¶

b() → _ods_ir[_ods_ir]¶

dst() → _ods_ir[_ods_ir]¶

class mlir.dialects._x86_ops_gen.DotInt8OpAdaptor(operands: list, attributes: OpAttributeMap)¶

class mlir.dialects._x86_ops_gen.DotInt8OpAdaptor(operands: list, opview: OpView)

Bases: _ods_ir

OPERATION_NAME = 'x86.avx.dot.i8'¶

w() → _ods_ir[_ods_ir]¶

a() → _ods_ir[_ods_ir]¶

b() → _ods_ir[_ods_ir]¶

mlir.dialects._x86_ops_gen.avx_dot_i8(w, a, b, *, results=None, loc=None, ip=None) → _ods_ir¶

class mlir.dialects._x86_ops_gen.DotOp(a, b, *, results=None, loc=None, ip=None)¶

Bases: _ods_ir

Computes the 4-way dot products of the lower and higher parts of the source vectors and broadcasts the two results to the lower and higher elements of the destination vector, respectively. Adding one element of the lower part to one element of the higher part in the destination vector yields the full dot product of the two source vectors.

Example:

%0 = x86.avx.intr.dot %a, %b : vector<8xf32>
%1 = vector.extract %0[%i0] : f32 from vector<8xf32>
%2 = vector.extract %0[%i4] : f32 from vector<8xf32>
%d = arith.addf %1, %2 : f32

OPERATION_NAME = 'x86.avx.intr.dot'¶

_ODS_REGIONS = (0, True)¶

a() → _ods_ir[_ods_ir]¶

b() → _ods_ir[_ods_ir]¶

res() → _ods_ir[_ods_ir]¶

class mlir.dialects._x86_ops_gen.DotOpAdaptor(operands: list, attributes: OpAttributeMap)¶

class mlir.dialects._x86_ops_gen.DotOpAdaptor(operands: list, opview: OpView)

Bases: _ods_ir

OPERATION_NAME = 'x86.avx.intr.dot'¶

a() → _ods_ir[_ods_ir]¶

b() → _ods_ir[_ods_ir]¶

mlir.dialects._x86_ops_gen.avx_intr_dot(a, b, *, results=None, loc=None, ip=None) → _ods_ir¶

class mlir.dialects._x86_ops_gen.MaskCompressOp(k, a, *, src=None, constant_src=None, results=None, loc=None, ip=None)¶

Bases: _ods_ir

The mask.compress op is an AVX512 specific op that can lower to the llvm.mask.compress instruction. Instead of src, a constant vector vector attribute constant_src may be specified. If neither src nor constant_src is specified, the remaining elements in the result vector are set to zero.

From the Intel Intrinsics Guide:¶

Contiguously store the active integer/floating-point elements in a (those with their respective bit set in writemask k) to dst, and pass through the remaining elements from src.

OPERATION_NAME = 'x86.avx512.mask.compress'¶

_ODS_REGIONS = (0, True)¶

k() → _ods_ir[_ods_ir]¶

a() → _ods_ir[_ods_ir]¶

src() → _ods_ir[_ods_ir] | None¶

constant_src() → _ods_ir | None¶

dst() → _ods_ir[_ods_ir]¶

class mlir.dialects._x86_ops_gen.MaskCompressOpAdaptor(operands: list, attributes: OpAttributeMap)¶

class mlir.dialects._x86_ops_gen.MaskCompressOpAdaptor(operands: list, opview: OpView)

Bases: _ods_ir

OPERATION_NAME = 'x86.avx512.mask.compress'¶

k() → _ods_ir[_ods_ir]¶

a() → _ods_ir[_ods_ir]¶

src() → _ods_ir[_ods_ir] | None¶

constant_src() → _ods_ir | None¶

mlir.dialects._x86_ops_gen.avx512_mask_compress(k, a, *, src=None, constant_src=None, results=None, loc=None, ip=None) → _ods_ir¶

class mlir.dialects._x86_ops_gen.MaskRndScaleOp(src, k, a, imm, rounding, *, results=None, loc=None, ip=None)¶

Bases: _ods_ir

The mask.rndscale op is an AVX512 specific op that can lower to the proper LLVMAVX512 operation: llvm.mask.rndscale.ps.512 or llvm.mask.rndscale.pd.512 instruction depending on the type of vectors it is applied to.

From the Intel Intrinsics Guide:¶

Round packed floating-point elements in a to the number of fraction bits specified by imm, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).

OPERATION_NAME = 'x86.avx512.mask.rndscale'¶

_ODS_REGIONS = (0, True)¶

src() → _ods_ir[_ods_ir]¶

k() → _ods_ir[_ods_ir]¶

a() → _ods_ir[_ods_ir]¶

imm() → _ods_ir¶

rounding() → _ods_ir[_ods_ir]¶

dst() → _ods_ir[_ods_ir]¶

class mlir.dialects._x86_ops_gen.MaskRndScaleOpAdaptor(operands: list, attributes: OpAttributeMap)¶

class mlir.dialects._x86_ops_gen.MaskRndScaleOpAdaptor(operands: list, opview: OpView)

Bases: _ods_ir

OPERATION_NAME = 'x86.avx512.mask.rndscale'¶

src() → _ods_ir[_ods_ir]¶

k() → _ods_ir[_ods_ir]¶

a() → _ods_ir[_ods_ir]¶

imm() → _ods_ir¶

rounding() → _ods_ir[_ods_ir]¶

mlir.dialects._x86_ops_gen.avx512_mask_rndscale(src, k, a, imm, rounding, *, results=None, loc=None, ip=None) → _ods_ir¶

class mlir.dialects._x86_ops_gen.MaskScaleFOp(src, a, b, k, rounding, *, results=None, loc=None, ip=None)¶

Bases: _ods_ir

The mask.scalef op is an AVX512 specific op that can lower to the proper LLVMAVX512 operation: llvm.mask.scalef.ps.512 or llvm.mask.scalef.pd.512 depending on the type of MLIR vectors it is applied to.

From the Intel Intrinsics Guide:¶

Scale the packed floating-point elements in a using values from b, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).

OPERATION_NAME = 'x86.avx512.mask.scalef'¶

_ODS_REGIONS = (0, True)¶

src() → _ods_ir[_ods_ir]¶

a() → _ods_ir[_ods_ir]¶

b() → _ods_ir[_ods_ir]¶

k() → _ods_ir¶

rounding() → _ods_ir[_ods_ir]¶

dst() → _ods_ir[_ods_ir]¶

class mlir.dialects._x86_ops_gen.MaskScaleFOpAdaptor(operands: list, attributes: OpAttributeMap)¶

class mlir.dialects._x86_ops_gen.MaskScaleFOpAdaptor(operands: list, opview: OpView)

Bases: _ods_ir

OPERATION_NAME = 'x86.avx512.mask.scalef'¶

src() → _ods_ir[_ods_ir]¶

a() → _ods_ir[_ods_ir]¶

b() → _ods_ir[_ods_ir]¶

k() → _ods_ir¶

rounding() → _ods_ir[_ods_ir]¶

mlir.dialects._x86_ops_gen.avx512_mask_scalef(src, a, b, k, rounding, *, results=None, loc=None, ip=None) → _ods_ir¶

class mlir.dialects._x86_ops_gen.RsqrtOp(a, *, results=None, loc=None, ip=None)¶

Bases: _ods_ir

OPERATION_NAME = 'x86.avx.rsqrt'¶

_ODS_REGIONS = (0, True)¶

a() → _ods_ir[_ods_ir]¶

b() → _ods_ir[_ods_ir]¶

class mlir.dialects._x86_ops_gen.RsqrtOpAdaptor(operands: list, attributes: OpAttributeMap)¶

class mlir.dialects._x86_ops_gen.RsqrtOpAdaptor(operands: list, opview: OpView)

Bases: _ods_ir

OPERATION_NAME = 'x86.avx.rsqrt'¶

a() → _ods_ir[_ods_ir]¶

mlir.dialects._x86_ops_gen.avx_rsqrt(a, *, results=None, loc=None, ip=None) → _ods_ir¶

class mlir.dialects._x86_ops_gen.TileLoadOp(res, base, indices, *, stride=None, loc=None, ip=None)¶

Bases: _ods_ir

Loads a tile from memory defined by a base and indices, with the shape defined by the 2-dim vector type of the result. The tile’s rows are populated by reading contiguous elements starting at the base. For each tile row, the base is incremented by stride number of elements.

The tile is loaded using the following indexing scheme:

for row in enumerate(tile_rows):
  mem_row = base[i0, i1, ..., iN + row * stride]
  for col in enumerate(tile_cols):
    tile[row, col] = mem_row[col]

If the stride is not provided, then the base buffer must be at least 2-dimensional, and the stride is automatically inferred and corresponds to the stride of the buffer’s second innermost dimension.

The operation is eventually lowered into the “tileloadd” instruction with the corresponding tile configuration.

With the write memory effect, each x86.amx.tile_load operation serves as a compilation hint to use a separate tile register.

Example:

// Tile load from a 2-D memref with implicit stride.
%0 = x86.amx.tile_load %arg0[%c0, %c0] : memref<?x?xi8> into !x86.amx.tile<16x64xi8>

// Tile load from a 1-D memref with explicit stride.
%0 = x86.amx.tile_load %arg0[%c0], %stride : memref<?xi8> into !x86.amx.tile<16x64xi8>

OPERATION_NAME = 'x86.amx.tile_load'¶

_ODS_OPERAND_SEGMENTS¶

_ODS_REGIONS = (0, True)¶

base() → _ods_ir[_ods_ir]¶

indices() → _ods_ir¶

stride() → _ods_ir[_ods_ir] | None¶

res() → _ods_ir¶

class mlir.dialects._x86_ops_gen.TileLoadOpAdaptor(operands: list, attributes: OpAttributeMap)¶

class mlir.dialects._x86_ops_gen.TileLoadOpAdaptor(operands: list, opview: OpView)

Bases: _ods_ir

OPERATION_NAME = 'x86.amx.tile_load'¶

base() → _ods_ir[_ods_ir]¶

indices() → _ods_ir¶

stride() → _ods_ir[_ods_ir] | None¶

mlir.dialects._x86_ops_gen.amx_tile_load(res, base, indices, *, stride=None, loc=None, ip=None) → _ods_ir¶

class mlir.dialects._x86_ops_gen.TileMulFOp(lhs, rhs, acc, *, results=None, loc=None, ip=None)¶

Bases: _ods_ir

Multiplies a “m x k” tile with a “k x n” tile and accumulates the results into a “m x n” destination tile. Supports “f32 <- bf16 x bf16” (with pairs of “bf16”).

The operation is eventually lowered into the “tdpbf16ps” instruction with the corresponding tile configuration.

Example:

%0 = x86.amx.tile_mulf %a, %b, %c
  : !x86.amx.tile<16x32xbf16>, !x86.amx.tile<16x32xbf16>, !x86.amx.tile<16x16xf32>

OPERATION_NAME = 'x86.amx.tile_mulf'¶

_ODS_REGIONS = (0, True)¶

lhs() → _ods_ir¶

rhs() → _ods_ir¶

acc() → _ods_ir¶

res() → _ods_ir¶

class mlir.dialects._x86_ops_gen.TileMulFOpAdaptor(operands: list, attributes: OpAttributeMap)¶

class mlir.dialects._x86_ops_gen.TileMulFOpAdaptor(operands: list, opview: OpView)

Bases: _ods_ir

OPERATION_NAME = 'x86.amx.tile_mulf'¶

lhs() → _ods_ir¶

rhs() → _ods_ir¶

acc() → _ods_ir¶

mlir.dialects._x86_ops_gen.amx_tile_mulf(lhs, rhs, acc, *, results=None, loc=None, ip=None) → _ods_ir¶

class mlir.dialects._x86_ops_gen.TileMulIOp(lhs, rhs, acc, *, isZextLhs=None, isZextRhs=None, results=None, loc=None, ip=None)¶

Bases: _ods_ir

Multiplies a “m x k” tile with a “k x n” tile and accumulates the results into a “m x n” destination tile. Supports all “si32 <- s/ui8 x s/ui8” combinations (4 bytes packed into dwords in the columns of both the source operand tiles; the zero or sign extension is specified with the attributes and default to sign extended).

The operation is eventually lowered into one of the “tdpbssd”, “tdpbsud”, “tdpbusd”, or “tdpbuud” instructions with the corresponding tile configuration.

Example:

%0 = x86.amx.tile_muli %a zext, %b zext, %c
  : !x86.amx.tile<16x64xi8>, !x86.amx.tile<16x64xi8>, !x86.amx.tile<16x16xi32>

OPERATION_NAME = 'x86.amx.tile_muli'¶

_ODS_REGIONS = (0, True)¶

lhs() → _ods_ir¶

rhs() → _ods_ir¶

acc() → _ods_ir¶

isZextLhs() → bool¶

isZextRhs() → bool¶

res() → _ods_ir¶

class mlir.dialects._x86_ops_gen.TileMulIOpAdaptor(operands: list, attributes: OpAttributeMap)¶

class mlir.dialects._x86_ops_gen.TileMulIOpAdaptor(operands: list, opview: OpView)

Bases: _ods_ir

OPERATION_NAME = 'x86.amx.tile_muli'¶

lhs() → _ods_ir¶

rhs() → _ods_ir¶

acc() → _ods_ir¶

isZextLhs() → bool¶

isZextRhs() → bool¶

mlir.dialects._x86_ops_gen.amx_tile_muli(lhs, rhs, acc, *, is_zext_lhs=None, is_zext_rhs=None, results=None, loc=None, ip=None) → _ods_ir¶

class mlir.dialects._x86_ops_gen.TileStoreOp(base, indices, val, *, stride=None, loc=None, ip=None)¶

Bases: _ods_ir

Stores a tile to memory defined by a base and indices, with the shape defined by the 2-dim vector type of the value. The tile’s rows are written contiguously to the buffer starting at the base. For each tile row, the base is incremented by stride number of elements.

The tile is stored using the following indexing scheme:

for row in enumerate(tile_rows):
  mem_row = base[i0, i1, ..., iN + row * stride]
  for col in enumerate(tile_cols):
    mem_row[col] = tile[row, col]

The operation is eventually lowered into the “tilestored” instruction with the corresponding tile configuration.

Example:

// Tile store to a 2-D memref with implicit stride.
x86.amx.tile_store %arg1[%c0, %c0], %0 : memref<?x?xi8>, !x86.amx.tile<16x64xi8>

// Tile store to a 1-D memref with explicit stride.
x86.amx.tile_store %arg1[%c0], %0, %stride : memref<?xi8>, !x86.amx.tile<16x64xi8>

OPERATION_NAME = 'x86.amx.tile_store'¶

_ODS_OPERAND_SEGMENTS¶

_ODS_REGIONS = (0, True)¶

base() → _ods_ir[_ods_ir]¶

indices() → _ods_ir¶

val() → _ods_ir¶

stride() → _ods_ir[_ods_ir] | None¶

class mlir.dialects._x86_ops_gen.TileStoreOpAdaptor(operands: list, attributes: OpAttributeMap)¶

class mlir.dialects._x86_ops_gen.TileStoreOpAdaptor(operands: list, opview: OpView)

Bases: _ods_ir

OPERATION_NAME = 'x86.amx.tile_store'¶

base() → _ods_ir[_ods_ir]¶

indices() → _ods_ir¶

val() → _ods_ir¶

stride() → _ods_ir[_ods_ir] | None¶

mlir.dialects._x86_ops_gen.amx_tile_store(base, indices, val, *, stride=None, loc=None, ip=None) → TileStoreOp¶

class mlir.dialects._x86_ops_gen.TileZeroOp(res, *, loc=None, ip=None)¶

Bases: _ods_ir

Zeroes the destination tile, with the shape defined by the 2-dim vector type of the result.

The operation is eventually lowered into the “tilezero” instruction with the corresponding tile configuration.

With the write memory effect, each x86.amx.tile_zero operation serves as a compilation hint to use a separate tile register.

Example:

%0 = x86.amx.tile_zero : !x86.amx.tile<16x16xbf16>

OPERATION_NAME = 'x86.amx.tile_zero'¶

_ODS_REGIONS = (0, True)¶

res() → _ods_ir¶

class mlir.dialects._x86_ops_gen.TileZeroOpAdaptor(operands: list, attributes: OpAttributeMap)¶

class mlir.dialects._x86_ops_gen.TileZeroOpAdaptor(operands: list, opview: OpView)

Bases: _ods_ir

OPERATION_NAME = 'x86.amx.tile_zero'¶

mlir.dialects._x86_ops_gen.amx_tile_zero(res, *, loc=None, ip=None) → _ods_ir¶

class mlir.dialects._x86_ops_gen.Vp2IntersectOp(a, b, *, results=None, loc=None, ip=None)¶

Bases: _ods_ir

The vp2intersect op is an AVX512 specific op that can lower to the proper LLVMAVX512 operation: llvm.vp2intersect.d.512 or llvm.vp2intersect.q.512 depending on the type of MLIR vectors it is applied to.

From the Intel Intrinsics Guide:¶

Compute intersection of packed integer vectors a and b, and store indication of match in the corresponding bit of two mask registers specified by k1 and k2. A match in corresponding elements of a and b is indicated by a set bit in the corresponding bit of the mask registers.

OPERATION_NAME = 'x86.avx512.vp2intersect'¶

_ODS_REGIONS = (0, True)¶

a() → _ods_ir[_ods_ir]¶

b() → _ods_ir[_ods_ir]¶

k1() → _ods_ir[_ods_ir]¶

k2() → _ods_ir[_ods_ir]¶

class mlir.dialects._x86_ops_gen.Vp2IntersectOpAdaptor(operands: list, attributes: OpAttributeMap)¶

class mlir.dialects._x86_ops_gen.Vp2IntersectOpAdaptor(operands: list, opview: OpView)

Bases: _ods_ir

OPERATION_NAME = 'x86.avx512.vp2intersect'¶

a() → _ods_ir[_ods_ir]¶

b() → _ods_ir[_ods_ir]¶

mlir.dialects._x86_ops_gen.avx512_vp2intersect(a, b, *, results=None, loc=None, ip=None) → _ods_ir¶